/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
//
// Alpha TLB
//
-
#ifdef DEBUG
- bool uncacheBit39 = false;
- bool uncacheBit40 = false;
+bool uncacheBit39 = false;
+bool uncacheBit40 = false;
#endif
-AlphaTlb::AlphaTlb(const string &name, int s)
+AlphaTLB::AlphaTLB(const string &name, int s)
: SimObject(name), size(s), nlu(0)
{
table = new AlphaISA::PTE[size];
memset(table, 0, sizeof(AlphaISA::PTE[size]));
}
-AlphaTlb::~AlphaTlb()
+AlphaTLB::~AlphaTLB()
{
if (table)
delete [] table;
// look up an entry in the TLB
AlphaISA::PTE *
-AlphaTlb::lookup(Addr vpn, uint8_t asn) const
+AlphaTLB::lookup(Addr vpn, uint8_t asn) const
{
DPRINTF(TLB, "lookup %#x\n", vpn);
void
-AlphaTlb::checkCacheability(MemReqPtr &req)
+AlphaTLB::checkCacheability(MemReqPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
* to catch a weird case where both are used, which shouldn't happen.
*/
- if (req->paddr & PA_UNCACHED_BIT_40 ||
- req->paddr & PA_UNCACHED_BIT_39) {
-#ifdef DEBUG
- if (req->paddr & PA_UNCACHED_BIT_40) {
- if(uncacheBit39)
- panic("Bit 40 access follows bit 39 access, PA=%x\n",
- req->paddr);
-
- uncacheBit40 = true;
- } else if (req->paddr & PA_UNCACHED_BIT_39) {
- if(uncacheBit40)
- panic("Bit 39 acceess follows bit 40 access, PA=%x\n",
- req->paddr);
-
- uncacheBit39 = true;
- }
+#ifdef ALPHA_TLASER
+ if (req->paddr & PA_UNCACHED_BIT_39) {
+#else
+ if (req->paddr & PA_UNCACHED_BIT_43) {
#endif
-
// IPR memory space not implemented
- if (PA_IPR_SPACE(req->paddr))
- if (!req->xc->misspeculating())
- panic("IPR memory space not implemented! PA=%x\n",
- req->paddr);
+ if (PA_IPR_SPACE(req->paddr)) {
+ if (!req->xc->misspeculating()) {
+ switch (req->paddr) {
+ case ULL(0xFFFFF00188):
+ req->data = 0;
+ break;
+
+ default:
+ panic("IPR memory space not implemented! PA=%x\n",
+ req->paddr);
+ }
+ }
+ } else {
+ // mark request as uncacheable
+ req->flags |= UNCACHEABLE;
- // mark request as uncacheable
- req->flags |= UNCACHEABLE;
+#ifndef ALPHA_TLASER
+ // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
+ req->paddr &= PA_UNCACHED_MASK;
+#endif
+ }
}
}
// insert a new TLB entry
void
-AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte)
+AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte)
{
if (table[nlu].valid) {
Addr oldvpn = table[nlu].tag;
}
void
-AlphaTlb::flushAll()
+AlphaTLB::flushAll()
{
memset(table, 0, sizeof(AlphaISA::PTE[size]));
lookupTable.clear();
}
void
-AlphaTlb::flushProcesses()
+AlphaTLB::flushProcesses()
{
PageTable::iterator i = lookupTable.begin();
PageTable::iterator end = lookupTable.end();
}
void
-AlphaTlb::flushAddr(Addr vaddr, uint8_t asn)
+AlphaTLB::flushAddr(Addr vaddr, uint8_t asn)
{
Addr vpn = VA_VPN(vaddr);
void
-AlphaTlb::serialize(ostream &os)
+AlphaTLB::serialize(ostream &os)
{
SERIALIZE_SCALAR(size);
SERIALIZE_SCALAR(nlu);
}
void
-AlphaTlb::unserialize(Checkpoint *cp, const string §ion)
+AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
{
UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(nlu);
//
// Alpha ITB
//
-AlphaItb::AlphaItb(const std::string &name, int size)
- : AlphaTlb(name, size)
+AlphaITB::AlphaITB(const std::string &name, int size)
+ : AlphaTLB(name, size)
{}
void
-AlphaItb::regStats()
+AlphaITB::regStats()
{
hits
.name(name() + ".hits")
}
void
-AlphaItb::fault(Addr pc, ExecContext *xc) const
+AlphaITB::fault(Addr pc, ExecContext *xc) const
{
uint64_t *ipr = xc->regs.ipr;
Fault
-AlphaItb::translate(MemReqPtr &req) const
+AlphaITB::translate(MemReqPtr &req) const
{
InternalProcReg *ipr = req->xc->regs.ipr;
if (!validVirtualAddress(req->vaddr)) {
fault(req->vaddr, req->xc);
acv++;
- return Itb_Acv_Fault;
+ return ITB_Acv_Fault;
}
- // Check for "superpage" mapping: when SP<1> is set, and
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
+
+ // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
+ // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
+#ifdef ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
- VA_SPACE(req->vaddr) == 2) {
+ VA_SPACE_EV5(req->vaddr) == 2) {
+#else
+ if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
+#endif
+
// only valid in kernel mode
if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
fault(req->vaddr, req->xc);
acv++;
- return Itb_Acv_Fault;
+ return ITB_Acv_Fault;
}
req->paddr = req->vaddr & PA_IMPL_MASK;
+#ifndef ALPHA_TLASER
// sign extend the physical address properly
- if (req->paddr & PA_UNCACHED_BIT_39 ||
- req->paddr & PA_UNCACHED_BIT_40)
- req->paddr |= 0xf0000000000ULL;
+ if (req->paddr & PA_UNCACHED_BIT_40)
+ req->paddr |= ULL(0xf0000000000);
else
- req->paddr &= 0xffffffffffULL;
+ req->paddr &= ULL(0xffffffffff);
+#endif
} else {
// not a physical address: need to look up pte
if (!pte) {
fault(req->vaddr, req->xc);
misses++;
- return Itb_Fault_Fault;
+ return ITB_Fault_Fault;
}
req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3);
// instruction access fault
fault(req->vaddr, req->xc);
acv++;
- return Itb_Acv_Fault;
+ return ITB_Acv_Fault;
}
hits++;
//
// Alpha DTB
//
-AlphaDtb::AlphaDtb(const std::string &name, int size)
- : AlphaTlb(name, size)
+AlphaDTB::AlphaDTB(const std::string &name, int size)
+ : AlphaTLB(name, size)
{}
void
-AlphaDtb::regStats()
+AlphaDTB::regStats()
{
read_hits
.name(name() + ".read_hits")
}
void
-AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
+AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
{
+ ExecContext *xc = req->xc;
+ Addr vaddr = req->vaddr;
uint64_t *ipr = xc->regs.ipr;
- // set fault address and flags
- if (!xc->misspeculating() && !xc->regs.intrlock) {
+ // Set fault address and flags. Even though we're modeling an
+ // EV5, we use the EV6 technique of not latching fault registers
+ // on VPTE loads (instead of locking the registers until IPR_VA is
+ // read, like the EV5). The EV6 approach is cleaner and seems to
+ // work with EV5 PAL code, but not the other way around.
+ if (!xc->misspeculating()
+ && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
// set VA register with faulting address
ipr[AlphaISA::IPR_VA] = vaddr;
// set MM_STAT register flags
- ipr[AlphaISA::IPR_MM_STAT] = (((xc->regs.opcode & 0x3f) << 11)
- | ((xc->regs.ra & 0x1f) << 6)
+ ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11)
+ | ((RA(xc->getInst()) & 0x1f) << 6)
| (flags & 0x3f));
// set VA_FORM register with faulting formatted address
ipr[AlphaISA::IPR_VA_FORM] =
ipr[AlphaISA::IPR_MVPTBR] | (VA_VPN(vaddr) << 3);
-
- // lock these registers until the VA register is read
- xc->regs.intrlock = true;
}
}
Fault
-AlphaDtb::translate(MemReqPtr &req, bool write) const
+AlphaDTB::translate(MemReqPtr &req, bool write) const
{
RegFile *regs = &req->xc->regs;
Addr pc = regs->pc;
} else {
// verify that this is a good virtual address
if (!validVirtualAddress(req->vaddr)) {
- fault(req->vaddr,
- ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK |
- MM_STAT_ACV_MASK),
- req->xc);
+ fault(req, ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK |
+ MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
- return Dtb_Fault_Fault;
+ return DTB_Fault_Fault;
}
- // Check for "superpage" mapping: when SP<1> is set, and
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
+ // Check for "superpage" mapping
+#ifdef ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
- VA_SPACE(req->vaddr) == 2) {
+ VA_SPACE_EV5(req->vaddr) == 2) {
+#else
+ if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
+#endif
// only valid in kernel mode
if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
AlphaISA::mode_kernel) {
- fault(req->vaddr,
- ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK),
- req->xc);
+ fault(req, ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
- return Dtb_Acv_Fault;
+ return DTB_Acv_Fault;
}
req->paddr = req->vaddr & PA_IMPL_MASK;
+#ifndef ALPHA_TLASER
// sign extend the physical address properly
- if (req->paddr & PA_UNCACHED_BIT_39 ||
- req->paddr & PA_UNCACHED_BIT_40)
- req->paddr |= 0xf0000000000ULL;
+ if (req->paddr & PA_UNCACHED_BIT_40)
+ req->paddr |= ULL(0xf0000000000);
else
- req->paddr &= 0xffffffffffULL;
+ req->paddr &= ULL(0xffffffffff);
+#endif
} else {
if (write)
if (!pte) {
// page fault
- fault(req->vaddr,
- ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK),
- req->xc);
+ fault(req,
+ (write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
}
if (write) {
if (!(pte->xwe & MODE2MASK(mode))) {
// declare the instruction access fault
- fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_ACV_MASK |
- (pte->fonw ? MM_STAT_FONW_MASK : 0),
- req->xc);
+ fault(req, (MM_STAT_WR_MASK | MM_STAT_ACV_MASK |
+ (pte->fonw ? MM_STAT_FONW_MASK : 0)));
write_acv++;
- return Dtb_Fault_Fault;
+ return DTB_Fault_Fault;
}
if (pte->fonw) {
- fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK,
- req->xc);
+ fault(req, MM_STAT_WR_MASK | MM_STAT_FONW_MASK);
write_acv++;
- return Dtb_Fault_Fault;
+ return DTB_Fault_Fault;
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
- fault(req->vaddr,
- MM_STAT_ACV_MASK |
- (pte->fonr ? MM_STAT_FONR_MASK : 0),
- req->xc);
+ fault(req, (MM_STAT_ACV_MASK |
+ (pte->fonr ? MM_STAT_FONR_MASK : 0)));
read_acv++;
- return Dtb_Acv_Fault;
+ return DTB_Acv_Fault;
}
if (pte->fonr) {
- fault(req->vaddr, MM_STAT_FONR_MASK, req->xc);
+ fault(req, MM_STAT_FONR_MASK);
read_acv++;
- return Dtb_Fault_Fault;
+ return DTB_Fault_Fault;
}
}
}
}
AlphaISA::PTE &
-AlphaTlb::index(bool advance)
+AlphaTLB::index(bool advance)
{
AlphaISA::PTE *pte = &table[nlu];
return *pte;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb)
+DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
Param<int> size;
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb)
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb)
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
INIT_PARAM_DFLT(size, "TLB size", 48)
-END_INIT_SIM_OBJECT_PARAMS(AlphaItb)
+END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
-CREATE_SIM_OBJECT(AlphaItb)
+CREATE_SIM_OBJECT(AlphaITB)
{
- return new AlphaItb(getInstanceName(), size);
+ return new AlphaITB(getInstanceName(), size);
}
-REGISTER_SIM_OBJECT("AlphaITB", AlphaItb)
+REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb)
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
Param<int> size;
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb)
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb)
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
INIT_PARAM_DFLT(size, "TLB size", 64)
-END_INIT_SIM_OBJECT_PARAMS(AlphaDtb)
+END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
-CREATE_SIM_OBJECT(AlphaDtb)
+CREATE_SIM_OBJECT(AlphaDTB)
{
- return new AlphaDtb(getInstanceName(), size);
+ return new AlphaDTB(getInstanceName(), size);
}
-REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb)
+REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
projects / gem5.git / blobdiff