Add a new operation class for IPR accesses, and have IPR-accessing

[gem5.git] / arch / alpha / alpha_memory.hh

diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index fc4d46191406ab9aa9e85034bb48feadbcef3c18..0d4b8d1f23b06ee560aae9ee6a46045459fe1b63 100644 (file)
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -31,13 +31,14 @@
 
 #include <map>
 
+#include "arch/alpha/isa_traits.hh"
+#include "base/statistics.hh"
 #include "mem/mem_req.hh"
 #include "sim/sim_object.hh"
-#include "base/statistics.hh"
 
 class ExecContext;
 
-class AlphaTlb : public SimObject
+class AlphaTLB : public SimObject
 {
   protected:
     typedef std::multimap<Addr, int> PageTable;
@@ -51,12 +52,12 @@ class AlphaTlb : public SimObject
     AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
   public:
-    AlphaTlb(const std::string &name, int size);
-    virtual ~AlphaTlb();
+    AlphaTLB(const std::string &name, int size);
+    virtual ~AlphaTLB();
 
     int getsize() const { return size; }
 
-    AlphaISA::PTE &index();
+    AlphaISA::PTE &index(bool advance = true);
     void insert(Addr vaddr, AlphaISA::PTE &pte);
 
     void flushAll();
@@ -66,59 +67,59 @@ class AlphaTlb : public SimObject
     // static helper functions... really EV5 VM traits
     static bool validVirtualAddress(Addr vaddr) {
         // unimplemented bits must be all 0 or all 1
-        Addr unimplBits = vaddr & VA_UNIMPL_MASK;
-        return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
+        Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
+        return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
     }
 
-    static void checkCacheability(MemReqPtr req);
+    static void checkCacheability(MemReqPtr &req);
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
-    virtual void unserialize(const IniFile *db, const std::string &section);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
 };
 
-class AlphaItb : public AlphaTlb
+class AlphaITB : public AlphaTLB
 {
   protected:
-    mutable Statistics::Scalar<> hits;
-    mutable Statistics::Scalar<> misses;
-    mutable Statistics::Scalar<> acv;
-    mutable Statistics::Formula accesses;
+    mutable Stats::Scalar<> hits;
+    mutable Stats::Scalar<> misses;
+    mutable Stats::Scalar<> acv;
+    mutable Stats::Formula accesses;
 
   protected:
     void fault(Addr pc, ExecContext *xc) const;
 
   public:
-    AlphaItb(const std::string &name, int size);
+    AlphaITB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req) const;
+    Fault translate(MemReqPtr &req) const;
 };
 
-class AlphaDtb : public AlphaTlb
+class AlphaDTB : public AlphaTLB
 {
   protected:
-    mutable Statistics::Scalar<> read_hits;
-    mutable Statistics::Scalar<> read_misses;
-    mutable Statistics::Scalar<> read_acv;
-    mutable Statistics::Scalar<> read_accesses;
-    mutable Statistics::Scalar<> write_hits;
-    mutable Statistics::Scalar<> write_misses;
-    mutable Statistics::Scalar<> write_acv;
-    mutable Statistics::Scalar<> write_accesses;
-    Statistics::Formula hits;
-    Statistics::Formula misses;
-    Statistics::Formula acv;
-    Statistics::Formula accesses;
+    mutable Stats::Scalar<> read_hits;
+    mutable Stats::Scalar<> read_misses;
+    mutable Stats::Scalar<> read_acv;
+    mutable Stats::Scalar<> read_accesses;
+    mutable Stats::Scalar<> write_hits;
+    mutable Stats::Scalar<> write_misses;
+    mutable Stats::Scalar<> write_acv;
+    mutable Stats::Scalar<> write_accesses;
+    Stats::Formula hits;
+    Stats::Formula misses;
+    Stats::Formula acv;
+    Stats::Formula accesses;
 
   protected:
-    void fault(Addr pc, uint64_t flags, ExecContext *xc) const;
+    void fault(MemReqPtr &req, uint64_t flags) const;
 
   public:
-    AlphaDtb(const std::string &name, int size);
+    AlphaDTB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req, bool write) const;
+    Fault translate(MemReqPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__