#include <map>
-#include "mem_req.hh"
-#include "sim_object.hh"
-#include "statistics.hh"
+#include "mem/mem_req.hh"
+#include "sim/sim_object.hh"
+#include "base/statistics.hh"
class ExecContext;
int getsize() const { return size; }
- AlphaISA::PTE &index();
+ AlphaISA::PTE &index(bool advance = true);
void insert(Addr vaddr, AlphaISA::PTE &pte);
void flushAll();
return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
}
- static void checkCacheability(MemReqPtr req);
+ static void checkCacheability(MemReqPtr &req);
// Checkpointing
- virtual void serialize();
- virtual void unserialize(IniFile &db, const std::string &category,
- ConfigNode *node);
-
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
};
class AlphaItb : public AlphaTlb
AlphaItb(const std::string &name, int size);
virtual void regStats();
- Fault translate(MemReqPtr req) const;
+ Fault translate(MemReqPtr &req) const;
};
class AlphaDtb : public AlphaTlb
AlphaDtb(const std::string &name, int size);
virtual void regStats();
- Fault translate(MemReqPtr req, bool write) const;
+ Fault translate(MemReqPtr &req, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__