Copy implementations

[gem5.git] / arch / alpha / alpha_memory.hh

diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index bfcd313e20708e3d8bd44f7f298e7b2da04c7fe6..999eec228a35ea48ec95938d78eabb61e666fb4e 100644 (file)
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -56,7 +56,7 @@ class AlphaTlb : public SimObject
 
     int getsize() const { return size; }
 
-    AlphaISA::PTE &index();
+    AlphaISA::PTE &index(bool advance = true);
     void insert(Addr vaddr, AlphaISA::PTE &pte);
 
     void flushAll();
@@ -70,7 +70,7 @@ class AlphaTlb : public SimObject
         return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
     }
 
-    static void checkCacheability(MemReqPtr req);
+    static void checkCacheability(MemReqPtr &req);
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
@@ -92,7 +92,7 @@ class AlphaItb : public AlphaTlb
     AlphaItb(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req) const;
+    Fault translate(MemReqPtr &req) const;
 };
 
 class AlphaDtb : public AlphaTlb
@@ -118,7 +118,7 @@ class AlphaDtb : public AlphaTlb
     AlphaDtb(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req, bool write) const;
+    Fault translate(MemReqPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__