Don't use magic numbers.

[gem5.git] / arch / alpha / ev5.cc

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index d2ca71b3a020da54db4a688c3d899855d3515d8f..8b95e8b3d825c3b09ca76e5d0842cba46a7b6f1f 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -6,8 +6,10 @@
 #include "base/kgdb.h"
 #include "base/remote_gdb.hh"
 #include "base/stats/events.hh"
+#include "cpu/base_cpu.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/fast_cpu/fast_cpu.hh"
+#include "kern/kernel_stats.hh"
 #include "sim/debug.hh"
 #include "sim/sim_events.hh"
 
@@ -162,11 +164,11 @@ AlphaISA::zeroRegisters(XC *xc)
 void
 ExecContext::ev5_trap(Fault fault)
 {
-    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
-    Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
+    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
+    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
 
     assert(!misspeculating());
-    kernelStats.fault(fault);
+    kernelStats->fault(fault);
 
     if (fault == Arithmetic_Fault)
         panic("Arithmetic traps are unimplemented!");
@@ -231,7 +233,7 @@ ExecContext::hwrei()
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
     if (!misspeculating()) {
-        kernelStats.hwrei();
+        kernelStats->hwrei();
 
         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
             AlphaISA::swap_palshadow(&regs, false);
@@ -414,7 +416,7 @@ ExecContext::setIpr(int idx, uint64_t val)
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
-        kernelStats.context(old, val);
+        kernelStats->context(old, val);
         break;
 
       case AlphaISA::IPR_DTB_PTE:
@@ -441,11 +443,14 @@ ExecContext::setIpr(int idx, uint64_t val)
 
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
-        kernelStats.swpipl(ipr[idx]);
+        kernelStats->swpipl(ipr[idx]);
         break;
 
       case AlphaISA::IPR_DTB_CM:
-        kernelStats.mode((val & 0x18) != 0);
+        if (val & 0x18)
+            kernelStats->mode(Kernel::user);
+        else
+            kernelStats->mode(Kernel::kernel);
 
       case AlphaISA::IPR_ICM:
         // only write two mode bits - processor mode
@@ -621,7 +626,7 @@ ExecContext::setIpr(int idx, uint64_t val)
 bool
 ExecContext::simPalCheck(int palFunc)
 {
-    kernelStats.callpal(palFunc);
+    kernelStats->callpal(palFunc);
 
     switch (palFunc) {
       case PAL::halt: