-/* $Id$ */
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
-#include "targetarch/alpha_memory.hh"
-#include "sim/annotation.hh"
-#ifdef DEBUG
-#include "sim/debug.hh"
-#endif
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
#include "cpu/exec_context.hh"
+#include "cpu/fast/cpu.hh"
+#include "kern/kernel_stats.hh"
+#include "sim/debug.hh"
#include "sim/sim_events.hh"
-#include "targetarch/isa_traits.hh"
-#include "base/remote_gdb.hh"
-#include "base/kgdb.h" // for ALPHA_KENTRY_IF
-#include "targetarch/osfpal.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
-#ifndef SYSTEM_EV5
-#error This code is only valid for EV5 systems
-#endif
+using namespace EV5;
////////////////////////////////////////////////////////////////////////
//
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
- regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
+ regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
regs->npc = regs->pc + sizeof(MachInst);
}
//
// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
//
-Addr
-AlphaISA::fault_addr[Num_Faults] = {
- 0x0000, /* No_Fault */
- 0x0001, /* Reset_Fault */
- 0x0401, /* Machine_Check_Fault */
- 0x0501, /* Arithmetic_Fault */
- 0x0101, /* Interrupt_Fault */
- 0x0201, /* Ndtb_Miss_Fault */
- 0x0281, /* Pdtb_Miss_Fault */
- 0x0301, /* Alignment_Fault */
- 0x0381, /* Dtb_Fault_Fault */
- 0x0381, /* Dtb_Acv_Fault */
- 0x0181, /* Itb_Miss_Fault */
- 0x0181, /* Itb_Fault_Fault */
- 0x0081, /* Itb_Acv_Fault */
- 0x0481, /* Unimplemented_Opcode_Fault */
- 0x0581, /* Fen_Fault */
- 0x2001, /* Pal_Fault */
- 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
+const Addr
+AlphaISA::fault_addr(Fault * fault)
+{
+ //Check for the system wide faults
+ if(fault == NoFault) return 0x0000;
+ else if(fault == MachineCheckFault) return 0x0401;
+ else if(fault == AlignmentFault) return 0x0301;
+ else if(fault == FakeMemFault) return 0x0000;
+ //Deal with the alpha specific faults
+ return ((AlphaFault*)fault)->vect;
};
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
uint64_t *ipr = regs->ipr;
bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
- ipr[IPR_PAL_BASE] = PAL_BASE;
+ ipr[IPR_PAL_BASE] = PalBase;
ipr[IPR_MCSR] = 0x6;
}
+template <class CPU>
+void
+AlphaISA::processInterrupts(CPU *cpu)
+{
+ //Check if there are any outstanding interrupts
+ //Handle the interrupts
+ int ipl = 0;
+ int summary = 0;
+ IntReg *ipr = cpu->getIprPtr();
+
+ cpu->checkInterrupts = false;
+
+ if (ipr[IPR_ASTRR])
+ panic("asynchronous traps not implemented\n");
+
+ if (ipr[IPR_SIRR]) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ uint64_t interrupts = cpu->intr_status();
+
+ if (interrupts) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ if (ipl && ipl > ipr[IPR_IPLR]) {
+ ipr[IPR_ISR] = summary;
+ ipr[IPR_INTID] = ipl;
+ cpu->trap(InterruptFault);
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ ipr[IPR_IPLR], ipl, summary);
+ }
+
+}
+
+template <class CPU>
void
-ExecContext::ev5_trap(Fault fault)
+AlphaISA::zeroRegisters(CPU *cpu)
{
+ // Insure ISA semantics
+ // (no longer very clean due to the change in setIntReg() in the
+ // cpu model. Consider changing later.)
+ cpu->xc->setIntReg(ZeroReg, 0);
+ cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
+}
+
+void
+ExecContext::ev5_trap(Fault * fault)
+{
+ DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
+ cpu->recordEvent(csprintf("Fault %s", fault->name));
+
assert(!misspeculating());
- kernelStats.fault(fault);
+ kernelStats->fault(fault);
- if (fault == Arithmetic_Fault)
+ if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
AlphaISA::InternalProcReg *ipr = regs.ipr;
// exception restart address
- if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
+ if (fault != InterruptFault || !inPalMode())
ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
- if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
- fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+ if (fault == PalFault || fault == ArithmeticFault /* ||
+ fault == InterruptFault && !inPalMode() */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
- if (!PC_PAL(regs.pc))
+ if (!inPalMode())
AlphaISA::swap_palshadow(®s, true);
- regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
+ regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
regs.npc = regs.pc + sizeof(MachInst);
-
- Annotate::Ev5Trap(this, fault);
}
void
-AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
+AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
{
InternalProcReg *ipr = regs->ipr;
- bool use_pc = (fault == No_Fault);
+ bool use_pc = (fault == NoFault);
- if (fault == Arithmetic_Fault)
+ if (fault == ArithmeticFault)
panic("arithmetic faults NYI...");
// compute exception restart address
- if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
+ if (use_pc || fault == PalFault || fault == ArithmeticFault) {
// traps... skip faulting instruction
ipr[IPR_EXC_ADDR] = regs->pc + 4;
} else {
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
- regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
+ regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
else
regs->npc = ipr[IPR_PAL_BASE] + pc;
// that's it! (orders of magnitude less painful than x86)
}
-bool AlphaISA::check_interrupts = false;
-
-Fault
+Fault *
ExecContext::hwrei()
{
uint64_t *ipr = regs.ipr;
- if (!PC_PAL(regs.pc))
- return Unimplemented_Opcode_Fault;
+ if (!inPalMode())
+ return UnimplementedOpcodeFault;
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
if (!misspeculating()) {
- kernelStats.hwrei();
+ kernelStats->hwrei();
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(®s, false);
- AlphaISA::check_interrupts = true;
+ cpu->checkInterrupts = true;
}
// FIXME: XXX check for interrupts? XXX
- return No_Fault;
+ return NoFault;
}
uint64_t
-ExecContext::readIpr(int idx, Fault &fault)
+ExecContext::readIpr(int idx, Fault * &fault)
{
uint64_t *ipr = regs.ipr;
uint64_t retval = 0; // return value, default 0
retval = ipr[idx];
break;
+ case AlphaISA::IPR_CC:
+ retval |= ipr[idx] & ULL(0xffffffff00000000);
+ retval |= cpu->curCycle() & ULL(0x00000000ffffffff);
+ break;
+
case AlphaISA::IPR_VA:
- // SFX: unlocks interrupt status registers
retval = ipr[idx];
- regs.intrlock = false;
break;
case AlphaISA::IPR_VA_FORM:
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = dtb->index();
+ AlphaISA::PTE &pte = dtb->index(!misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
- fault = Unimplemented_Opcode_Fault;
+ fault = UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = Unimplemented_Opcode_Fault;
+ fault = UnimplementedOpcodeFault;
break;
}
int break_ipl = -1;
#endif
-Fault
+Fault *
ExecContext::setIpr(int idx, uint64_t val)
{
uint64_t *ipr = regs.ipr;
+ uint64_t old;
if (misspeculating())
- return No_Fault;
+ return NoFault;
switch (idx) {
case AlphaISA::IPR_PALtemp0:
case AlphaISA::IPR_PAL_BASE:
case AlphaISA::IPR_IC_PERR_STAT:
case AlphaISA::IPR_DC_PERR_STAT:
- case AlphaISA::IPR_CC_CTL:
- case AlphaISA::IPR_CC:
case AlphaISA::IPR_PMCTR:
// write entire quad w/ no side-effect
ipr[idx] = val;
break;
+ case AlphaISA::IPR_CC_CTL:
+ // This IPR resets the cycle counter. We assume this only
+ // happens once... let's verify that.
+ assert(ipr[idx] == 0);
+ ipr[idx] = 1;
+ break;
+
+ case AlphaISA::IPR_CC:
+ // This IPR only writes the upper 64 bits. It's ok to write
+ // all 64 here since we mask out the lower 32 in rpcc (see
+ // isa_desc).
+ ipr[idx] = val;
+ break;
+
case AlphaISA::IPR_PALtemp23:
// write entire quad w/ no side-effect
+ old = ipr[idx];
ipr[idx] = val;
- kernelStats.context(ipr[idx]);
- Annotate::Context(this);
+ kernelStats->context(old, val);
break;
case AlphaISA::IPR_DTB_PTE:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
- kernelStats.swpipl(ipr[idx]);
- Annotate::IPL(this, val & 0x1f);
+ kernelStats->swpipl(ipr[idx]);
break;
case AlphaISA::IPR_DTB_CM:
- Annotate::ChangeMode(this, (val & 0x18) != 0);
- kernelStats.mode((val & 0x18) != 0);
+ if (val & 0x18)
+ kernelStats->mode(Kernel::user);
+ else
+ kernelStats->mode(Kernel::kernel);
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
default:
// invalid IPR
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
}
// no error...
- return No_Fault;
+ return NoFault;
}
/**
bool
ExecContext::simPalCheck(int palFunc)
{
- kernelStats.callpal(palFunc);
+ kernelStats->callpal(palFunc);
switch (palFunc) {
case PAL::halt:
return true;
}
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::processInterrupts(FastCPU *xc);
+
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::zeroRegisters(FastCPU *xc);
+
#endif // FULL_SYSTEM
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