// Machine dependent functions
//
void
-AlphaISA::init(void *mem, RegFile *regs)
+AlphaISA::initCPU(RegFile *regs)
{
- ipr_init(mem, regs);
-}
+ initIPRs(regs);
+ // CPU comes up with PAL regs enabled
+ swap_palshadow(regs, true);
-void
-m5_exit()
-{
- static SimExitEvent event("m5_exit instruction encountered");
+ regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
+ regs->npc = regs->pc + sizeof(MachInst);
}
////////////////////////////////////////////////////////////////////////
//
//
void
-AlphaISA::ipr_init(void *mem, RegFile *regs)
+AlphaISA::initIPRs(RegFile *regs)
{
uint64_t *ipr = regs->ipr;
bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
ipr[IPR_PAL_BASE] = PAL_BASE;
+ ipr[IPR_MCSR] = 0x6;
}
if (!PC_PAL(regs.pc))
return Unimplemented_Opcode_Fault;
- kernelStats.hwrei();
-
- regs.npc = ipr[AlphaISA::IPR_EXC_ADDR];
+ setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
if (!misspeculating()) {
+ kernelStats.hwrei();
+
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(®s, false);
case AlphaISA::IPR_VA:
// SFX: unlocks interrupt status registers
retval = ipr[idx];
- regs.intrlock = false;
+
+ if (!misspeculating())
+ regs.intrlock = false;
break;
case AlphaISA::IPR_VA_FORM:
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = dtb->index();
+ AlphaISA::PTE &pte = dtb->index(!misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
switch (palFunc) {
case PAL::halt:
- if (!misspeculating()) {
- setStatus(Halted);
- if (--System::numSystemsRunning == 0)
- new SimExitEvent("all cpus halted");
- }
+ halt();
+ if (--System::numSystemsRunning == 0)
+ new SimExitEvent("all cpus halted");
break;
case PAL::bpt:
case PAL::bugchk:
- if (system->remoteGDB->trap(ALPHA_KENTRY_IF))
+ if (system->breakpoint())
return false;
break;
}