Copy implementations

[gem5.git] / arch / alpha / ev5.cc

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 7330d7ce0094254519fb1c385f26f0a306e0e698..aaa81a58d8e110467ac537ec9c6ffc4faf31fd93 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -54,12 +54,6 @@ AlphaISA::initCPU(RegFile *regs)
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
-void
-m5_exit()
-{
-    static SimExitEvent event("m5_exit instruction encountered");
-}
-
 ////////////////////////////////////////////////////////////////////////
 //
 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
@@ -174,11 +168,11 @@ ExecContext::hwrei()
     if (!PC_PAL(regs.pc))
         return Unimplemented_Opcode_Fault;
 
-    kernelStats.hwrei();
-
-    regs.npc = ipr[AlphaISA::IPR_EXC_ADDR];
+    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
     if (!misspeculating()) {
+        kernelStats.hwrei();
+
         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
             AlphaISA::swap_palshadow(&regs, false);
 
@@ -246,7 +240,9 @@ ExecContext::readIpr(int idx, Fault &fault)
       case AlphaISA::IPR_VA:
         // SFX: unlocks interrupt status registers
         retval = ipr[idx];
-        regs.intrlock = false;
+
+        if (!misspeculating())
+            regs.intrlock = false;
         break;
 
       case AlphaISA::IPR_VA_FORM:
@@ -259,7 +255,7 @@ ExecContext::readIpr(int idx, Fault &fault)
 
       case AlphaISA::IPR_DTB_PTE:
         {
-            AlphaISA::PTE &pte = dtb->index();
+            AlphaISA::PTE &pte = dtb->index(!misspeculating());
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -557,11 +553,9 @@ ExecContext::simPalCheck(int palFunc)
 
     switch (palFunc) {
       case PAL::halt:
-        if (!misspeculating()) {
-            setStatus(Halted);
-            if (--System::numSystemsRunning == 0)
-                new SimExitEvent("all cpus halted");
-        }
+        halt();
+        if (--System::numSystemsRunning == 0)
+            new SimExitEvent("all cpus halted");
         break;
 
       case PAL::bpt: