case AlphaISA::IPR_VA:
// SFX: unlocks interrupt status registers
retval = ipr[idx];
- regs.intrlock = false;
+
+ if (!misspeculating())
+ regs.intrlock = false;
break;
case AlphaISA::IPR_VA_FORM:
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = dtb->index();
+ AlphaISA::PTE &pte = dtb->index(!misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
switch (palFunc) {
case PAL::halt:
- if (!misspeculating()) {
- setStatus(Halted);
- if (--System::numSystemsRunning == 0)
- new SimExitEvent("all cpus halted");
- }
+ halt();
+ if (--System::numSystemsRunning == 0)
+ new SimExitEvent("all cpus halted");
break;
case PAL::bpt:
case PAL::bugchk:
- if (!misspeculating() && system->breakpoint())
+ if (system->breakpoint())
return false;
break;
}