cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
}
-void
-ExecContext::ev5_temp_trap(Fault fault)
-{
- DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
- cpu->recordEvent(csprintf("Fault %s", fault->name()));
-
- assert(!misspeculating());
- kernelStats->fault(fault);
-
- if (fault->isA<ArithmeticFault>())
- panic("Arithmetic traps are unimplemented!");
-
- // exception restart address
- if (!fault->isA<InterruptFault>() || !inPalMode())
- setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
-
- if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
- fault == InterruptFault && !inPalMode() */) {
- // traps... skip faulting instruction.
- setMiscReg(AlphaISA::IPR_EXC_ADDR,
- readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
- }
-
- if (!inPalMode())
- AlphaISA::swap_palshadow(®s, true);
-
- regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
- (dynamic_cast<AlphaFault *>(fault.get()))->vect();
- regs.npc = regs.pc + sizeof(MachInst);
-}
-
-
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{
- bool use_pc = (fault == NoFault);
+/* bool use_pc = (fault == NoFault);
if (fault->isA<ArithmeticFault>())
panic("arithmetic faults NYI...");
(dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
-
+*/
// that's it! (orders of magnitude less painful than x86)
}