-/* $Id$ */
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
-#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/tlb.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/osfpal.hh"
#include "base/kgdb.h"
#include "base/remote_gdb.hh"
#include "base/stats/events.hh"
-#include "cpu/base_cpu.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
#include "cpu/exec_context.hh"
-#include "cpu/fast_cpu/fast_cpu.hh"
+#include "cpu/fast/cpu.hh"
+#include "kern/kernel_stats.hh"
#include "sim/debug.hh"
#include "sim/sim_events.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
-#ifndef SYSTEM_EV5
-#error This code is only valid for EV5 systems
-#endif
+using namespace EV5;
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
//
void
-AlphaISA::initCPU(RegFile *regs)
+AlphaISA::initCPU(RegFile *regs, int cpuId)
{
- initIPRs(regs);
+ initIPRs(®s->miscRegs, cpuId);
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
- regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
+ regs->intRegFile[16] = cpuId;
+ regs->intRegFile[0] = cpuId;
+
+ regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + (new ResetFault)->vect();
regs->npc = regs->pc + sizeof(MachInst);
}
-////////////////////////////////////////////////////////////////////////
-//
-// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
-//
-Addr
-AlphaISA::fault_addr[Num_Faults] = {
- 0x0000, /* No_Fault */
- 0x0001, /* Reset_Fault */
- 0x0401, /* Machine_Check_Fault */
- 0x0501, /* Arithmetic_Fault */
- 0x0101, /* Interrupt_Fault */
- 0x0201, /* Ndtb_Miss_Fault */
- 0x0281, /* Pdtb_Miss_Fault */
- 0x0301, /* Alignment_Fault */
- 0x0381, /* DTB_Fault_Fault */
- 0x0381, /* DTB_Acv_Fault */
- 0x0181, /* ITB_Miss_Fault */
- 0x0181, /* ITB_Fault_Fault */
- 0x0081, /* ITB_Acv_Fault */
- 0x0481, /* Unimplemented_Opcode_Fault */
- 0x0581, /* Fen_Fault */
- 0x2001, /* Pal_Fault */
- 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
-};
-
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
//
//
void
-AlphaISA::initIPRs(RegFile *regs)
+AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
{
- uint64_t *ipr = regs->ipr;
+ miscRegs->clearIprs();
- bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
- ipr[IPR_PAL_BASE] = PAL_BASE;
- ipr[IPR_MCSR] = 0x6;
+ miscRegs->setReg(IPR_PAL_BASE, PalBase);
+ miscRegs->setReg(IPR_MCSR, 0x6);
+ miscRegs->setReg(IPR_PALtemp16, cpuId);
}
-template <class XC>
+template <class CPU>
void
-AlphaISA::processInterrupts(XC *xc)
+AlphaISA::processInterrupts(CPU *cpu)
{
//Check if there are any outstanding interrupts
//Handle the interrupts
int ipl = 0;
int summary = 0;
- IntReg *ipr = xc->getIprPtr();
- check_interrupts = 0;
+ cpu->checkInterrupts = false;
- if (ipr[IPR_ASTRR])
+ if (cpu->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
- if (ipr[IPR_SIRR]) {
+ if (cpu->readMiscReg(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+ if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
}
}
- uint64_t interrupts = xc->intr_status();
+ uint64_t interrupts = cpu->intr_status();
if (interrupts) {
for (int i = INTLEVEL_EXTERNAL_MIN;
}
}
- if (ipl && ipl > ipr[IPR_IPLR]) {
- ipr[IPR_ISR] = summary;
- ipr[IPR_INTID] = ipl;
- xc->trap(Interrupt_Fault);
+ if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
+ cpu->setMiscReg(IPR_ISR, summary);
+ cpu->setMiscReg(IPR_INTID, ipl);
+ cpu->trap(new InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- ipr[IPR_IPLR], ipl, summary);
+ cpu->readMiscReg(IPR_IPLR), ipl, summary);
}
}
-template <class XC>
+template <class CPU>
void
-AlphaISA::zeroRegisters(XC *xc)
+AlphaISA::zeroRegisters(CPU *cpu)
{
// Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
- xc->xc->setIntReg(ZeroReg, 0);
- xc->xc->setFloatRegDouble(ZeroReg, 0.0);
-}
-
-void
-ExecContext::ev5_trap(Fault fault)
-{
- DPRINTF(Fault, "Fault %s\n", FaultName(fault));
- cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
-
- assert(!misspeculating());
- kernelStats.fault(fault);
-
- if (fault == Arithmetic_Fault)
- panic("Arithmetic traps are unimplemented!");
-
- AlphaISA::InternalProcReg *ipr = regs.ipr;
-
- // exception restart address
- if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
- ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
-
- if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
- fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
- // traps... skip faulting instruction
- ipr[AlphaISA::IPR_EXC_ADDR] += 4;
- }
-
- if (!PC_PAL(regs.pc))
- AlphaISA::swap_palshadow(®s, true);
-
- regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
- regs.npc = regs.pc + sizeof(MachInst);
+ cpu->xc->setIntReg(ZeroReg, 0);
+ cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
}
-
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{
- InternalProcReg *ipr = regs->ipr;
- bool use_pc = (fault == No_Fault);
+/* bool use_pc = (fault == NoFault);
- if (fault == Arithmetic_Fault)
+ if (fault->isA<ArithmeticFault>())
panic("arithmetic faults NYI...");
// compute exception restart address
- if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
+ if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
// traps... skip faulting instruction
- ipr[IPR_EXC_ADDR] = regs->pc + 4;
+ regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
} else {
// fault, post fault at excepting instruction
- ipr[IPR_EXC_ADDR] = regs->pc;
+ regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
}
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
- regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
+ regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
- regs->npc = ipr[IPR_PAL_BASE] + pc;
-
+ regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
+*/
// that's it! (orders of magnitude less painful than x86)
}
-bool AlphaISA::check_interrupts = false;
-
Fault
ExecContext::hwrei()
{
- uint64_t *ipr = regs.ipr;
-
- if (!PC_PAL(regs.pc))
- return Unimplemented_Opcode_Fault;
+ if (!inPalMode())
+ return new UnimplementedOpcodeFault;
- setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+ setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
if (!misspeculating()) {
- kernelStats.hwrei();
+ kernelStats->hwrei();
- if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+ if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
AlphaISA::swap_palshadow(®s, false);
- AlphaISA::check_interrupts = true;
+ cpu->checkInterrupts = true;
}
// FIXME: XXX check for interrupts? XXX
- return No_Fault;
+ return NoFault;
+}
+
+void
+AlphaISA::MiscRegFile::clearIprs()
+{
+ bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
}
-uint64_t
-ExecContext::readIpr(int idx, Fault &fault)
+AlphaISA::MiscReg
+AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
{
- uint64_t *ipr = regs.ipr;
uint64_t retval = 0; // return value, default 0
switch (idx) {
case AlphaISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= curTick & ULL(0x00000000ffffffff);
+ retval |= xc->cpu->curCycle() & ULL(0x00000000ffffffff);
break;
case AlphaISA::IPR_VA:
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = dtb->index(!misspeculating());
+ AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
- fault = Unimplemented_Opcode_Fault;
+ fault = new UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = Unimplemented_Opcode_Fault;
+ fault = new UnimplementedOpcodeFault;
break;
}
#endif
Fault
-ExecContext::setIpr(int idx, uint64_t val)
+AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
{
- uint64_t *ipr = regs.ipr;
uint64_t old;
- if (misspeculating())
- return No_Fault;
+ if (xc->misspeculating())
+ return NoFault;
switch (idx) {
case AlphaISA::IPR_PALtemp0:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
- kernelStats.context(old, val);
+ xc->kernelStats->context(old, val);
break;
case AlphaISA::IPR_DTB_PTE:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
- kernelStats.swpipl(ipr[idx]);
+ xc->kernelStats->swpipl(ipr[idx]);
break;
case AlphaISA::IPR_DTB_CM:
- kernelStats.mode((val & 0x18) != 0);
+ if (val & 0x18)
+ xc->kernelStats->mode(Kernel::user);
+ else
+ xc->kernelStats->mode(Kernel::kernel);
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return Unimplemented_Opcode_Fault;
+ return new UnimplementedOpcodeFault;
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
// really a control write
ipr[idx] = 0;
- dtb->flushAll();
+ xc->dtb->flushAll();
break;
case AlphaISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
- dtb->flushProcesses();
+ xc->dtb->flushProcesses();
break;
case AlphaISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
- dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
- dtb->insert(val, pte);
+ xc->dtb->insert(val, pte);
}
break;
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
- itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
+ xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
}
break;
// really a control write
ipr[idx] = 0;
- itb->flushAll();
+ xc->itb->flushAll();
break;
case AlphaISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
- itb->flushProcesses();
+ xc->itb->flushProcesses();
break;
case AlphaISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
- itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+ xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
// invalid IPR
- return Unimplemented_Opcode_Fault;
+ return new UnimplementedOpcodeFault;
}
// no error...
- return No_Fault;
+ return NoFault;
}
/**
bool
ExecContext::simPalCheck(int palFunc)
{
- kernelStats.callpal(palFunc);
+ kernelStats->callpal(palFunc);
switch (palFunc) {
case PAL::halt:
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