Merge zizzer:/bk/linux into zeep.eecs.umich.edu:/z/saidi/work/m5-linux

[gem5.git] / arch / alpha / ev5.cc

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 468acdc55fa79d0468ff7171bd28d63b3514c425..d2ca71b3a020da54db4a688c3d899855d3515d8f 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -1,16 +1,15 @@
 /* $Id$ */
 
-#include "targetarch/alpha_memory.hh"
-#include "sim/annotation.hh"
-#ifdef DEBUG
-#include "sim/debug.hh"
-#endif
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
 #include "cpu/exec_context.hh"
+#include "cpu/fast_cpu/fast_cpu.hh"
+#include "sim/debug.hh"
 #include "sim/sim_events.hh"
-#include "targetarch/isa_traits.hh"
-#include "base/remote_gdb.hh"
-#include "base/kgdb.h" // for ALPHA_KENTRY_IF
-#include "targetarch/osfpal.hh"
 
 #ifdef FULL_SYSTEM
 
@@ -100,9 +99,72 @@ AlphaISA::initIPRs(RegFile *regs)
 }
 
 
+template <class XC>
+void
+AlphaISA::processInterrupts(XC *xc)
+{
+    //Check if there are any outstanding interrupts
+    //Handle the interrupts
+    int ipl = 0;
+    int summary = 0;
+    IntReg *ipr = xc->getIprPtr();
+
+    check_interrupts = 0;
+
+    if (ipr[IPR_ASTRR])
+        panic("asynchronous traps not implemented\n");
+
+    if (ipr[IPR_SIRR]) {
+        for (int i = INTLEVEL_SOFTWARE_MIN;
+             i < INTLEVEL_SOFTWARE_MAX; i++) {
+            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    uint64_t interrupts = xc->intr_status();
+
+    if (interrupts) {
+        for (int i = INTLEVEL_EXTERNAL_MIN;
+             i < INTLEVEL_EXTERNAL_MAX; i++) {
+            if (interrupts & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = i;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    if (ipl && ipl > ipr[IPR_IPLR]) {
+        ipr[IPR_ISR] = summary;
+        ipr[IPR_INTID] = ipl;
+        xc->trap(Interrupt_Fault);
+        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+                ipr[IPR_IPLR], ipl, summary);
+    }
+
+}
+
+template <class XC>
+void
+AlphaISA::zeroRegisters(XC *xc)
+{
+    // Insure ISA semantics
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    xc->xc->setIntReg(ZeroReg, 0);
+    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
+}
+
 void
 ExecContext::ev5_trap(Fault fault)
 {
+    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
+    Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
+
     assert(!misspeculating());
     kernelStats.fault(fault);
 
@@ -126,8 +188,6 @@ ExecContext::ev5_trap(Fault fault)
 
     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
     regs.npc = regs.pc + sizeof(MachInst);
-
-    Annotate::Ev5Trap(this, fault);
 }
 
 
@@ -243,11 +303,7 @@ ExecContext::readIpr(int idx, Fault &fault)
         break;
 
       case AlphaISA::IPR_VA:
-        // SFX: unlocks interrupt status registers
         retval = ipr[idx];
-
-        if (!misspeculating())
-            regs.intrlock = false;
         break;
 
       case AlphaISA::IPR_VA_FORM:
@@ -359,7 +415,6 @@ ExecContext::setIpr(int idx, uint64_t val)
         old = ipr[idx];
         ipr[idx] = val;
         kernelStats.context(old, val);
-        Annotate::Context(this);
         break;
 
       case AlphaISA::IPR_DTB_PTE:
@@ -387,11 +442,9 @@ ExecContext::setIpr(int idx, uint64_t val)
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
         kernelStats.swpipl(ipr[idx]);
-        Annotate::IPL(this, val & 0x1f);
         break;
 
       case AlphaISA::IPR_DTB_CM:
-        Annotate::ChangeMode(this, (val & 0x18) != 0);
         kernelStats.mode((val & 0x18) != 0);
 
       case AlphaISA::IPR_ICM:
@@ -587,4 +640,12 @@ ExecContext::simPalCheck(int palFunc)
     return true;
 }
 
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::processInterrupts(FastCPU *xc);
+
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::zeroRegisters(FastCPU *xc);
+
 #endif // FULL_SYSTEM