/* $Id$ */
-#include "targetarch/alpha_memory.hh"
-#include "sim/annotation.hh"
-#ifdef DEBUG
-#include "sim/debug.hh"
-#endif
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
#include "cpu/exec_context.hh"
+#include "cpu/fast_cpu/fast_cpu.hh"
+#include "sim/debug.hh"
#include "sim/sim_events.hh"
-#include "targetarch/isa_traits.hh"
-#include "base/remote_gdb.hh"
-#include "base/kgdb.h" // for ALPHA_KENTRY_IF
-#include "targetarch/osfpal.hh"
#ifdef FULL_SYSTEM
0x0201, /* Ndtb_Miss_Fault */
0x0281, /* Pdtb_Miss_Fault */
0x0301, /* Alignment_Fault */
- 0x0381, /* Dtb_Fault_Fault */
- 0x0381, /* Dtb_Acv_Fault */
- 0x0181, /* Itb_Miss_Fault */
- 0x0181, /* Itb_Fault_Fault */
- 0x0081, /* Itb_Acv_Fault */
+ 0x0381, /* DTB_Fault_Fault */
+ 0x0381, /* DTB_Acv_Fault */
+ 0x0181, /* ITB_Miss_Fault */
+ 0x0181, /* ITB_Fault_Fault */
+ 0x0081, /* ITB_Acv_Fault */
0x0481, /* Unimplemented_Opcode_Fault */
0x0581, /* Fen_Fault */
0x2001, /* Pal_Fault */
}
+template <class XC>
+void
+AlphaISA::processInterrupts(XC *xc)
+{
+ //Check if there are any outstanding interrupts
+ //Handle the interrupts
+ int ipl = 0;
+ int summary = 0;
+ IntReg *ipr = xc->getIprPtr();
+
+ check_interrupts = 0;
+
+ if (ipr[IPR_ASTRR])
+ panic("asynchronous traps not implemented\n");
+
+ if (ipr[IPR_SIRR]) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ uint64_t interrupts = xc->intr_status();
+
+ if (interrupts) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ if (ipl && ipl > ipr[IPR_IPLR]) {
+ ipr[IPR_ISR] = summary;
+ ipr[IPR_INTID] = ipl;
+ xc->trap(Interrupt_Fault);
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ ipr[IPR_IPLR], ipl, summary);
+ }
+
+}
+
+template <class XC>
+void
+AlphaISA::zeroRegisters(XC *xc)
+{
+ // Insure ISA semantics
+ // (no longer very clean due to the change in setIntReg() in the
+ // cpu model. Consider changing later.)
+ xc->xc->setIntReg(ZeroReg, 0);
+ xc->xc->setFloatRegDouble(ZeroReg, 0.0);
+}
+
void
ExecContext::ev5_trap(Fault fault)
{
+ DPRINTF(Fault, "Fault %s\n", FaultName(fault));
+ Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
+
assert(!misspeculating());
kernelStats.fault(fault);
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
regs.npc = regs.pc + sizeof(MachInst);
-
- Annotate::Ev5Trap(this, fault);
}
retval = ipr[idx];
break;
+ case AlphaISA::IPR_CC:
+ retval |= ipr[idx] & ULL(0xffffffff00000000);
+ retval |= curTick & ULL(0x00000000ffffffff);
+ break;
+
case AlphaISA::IPR_VA:
- // SFX: unlocks interrupt status registers
retval = ipr[idx];
- regs.intrlock = false;
break;
case AlphaISA::IPR_VA_FORM:
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = dtb->index();
+ AlphaISA::PTE &pte = dtb->index(!misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
ExecContext::setIpr(int idx, uint64_t val)
{
uint64_t *ipr = regs.ipr;
+ uint64_t old;
if (misspeculating())
return No_Fault;
case AlphaISA::IPR_PAL_BASE:
case AlphaISA::IPR_IC_PERR_STAT:
case AlphaISA::IPR_DC_PERR_STAT:
- case AlphaISA::IPR_CC_CTL:
- case AlphaISA::IPR_CC:
case AlphaISA::IPR_PMCTR:
// write entire quad w/ no side-effect
ipr[idx] = val;
break;
+ case AlphaISA::IPR_CC_CTL:
+ // This IPR resets the cycle counter. We assume this only
+ // happens once... let's verify that.
+ assert(ipr[idx] == 0);
+ ipr[idx] = 1;
+ break;
+
+ case AlphaISA::IPR_CC:
+ // This IPR only writes the upper 64 bits. It's ok to write
+ // all 64 here since we mask out the lower 32 in rpcc (see
+ // isa_desc).
+ ipr[idx] = val;
+ break;
+
case AlphaISA::IPR_PALtemp23:
// write entire quad w/ no side-effect
+ old = ipr[idx];
ipr[idx] = val;
- kernelStats.context(ipr[idx]);
- Annotate::Context(this);
+ kernelStats.context(old, val);
break;
case AlphaISA::IPR_DTB_PTE:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
kernelStats.swpipl(ipr[idx]);
- Annotate::IPL(this, val & 0x1f);
break;
case AlphaISA::IPR_DTB_CM:
- Annotate::ChangeMode(this, (val & 0x18) != 0);
kernelStats.mode((val & 0x18) != 0);
case AlphaISA::IPR_ICM:
switch (palFunc) {
case PAL::halt:
- if (!misspeculating()) {
- setStatus(Halted);
- if (--System::numSystemsRunning == 0)
- new SimExitEvent("all cpus halted");
- }
+ halt();
+ if (--System::numSystemsRunning == 0)
+ new SimExitEvent("all cpus halted");
break;
case PAL::bpt:
case PAL::bugchk:
- if (!misspeculating() && system->breakpoint())
+ if (system->breakpoint())
return false;
break;
}
return true;
}
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::processInterrupts(FastCPU *xc);
+
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::zeroRegisters(FastCPU *xc);
+
#endif // FULL_SYSTEM
projects / gem5.git / blobdiff