Merge zizzer:/bk/linux into zeep.eecs.umich.edu:/z/saidi/work/m5-linux

[gem5.git] / arch / alpha / ev5.cc

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e88f6d0a3a3dca0fe5f61af836e11160f52a1b85..d2ca71b3a020da54db4a688c3d899855d3515d8f 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -153,13 +153,16 @@ void
 AlphaISA::zeroRegisters(XC *xc)
 {
     // Insure ISA semantics
-    xc->setIntReg(ZeroReg, 0);
-    xc->setFloatRegDouble(ZeroReg, 0.0);
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    xc->xc->setIntReg(ZeroReg, 0);
+    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
 }
 
 void
 ExecContext::ev5_trap(Fault fault)
 {
+    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
     Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
 
     assert(!misspeculating());
@@ -300,11 +303,7 @@ ExecContext::readIpr(int idx, Fault &fault)
         break;
 
       case AlphaISA::IPR_VA:
-        // SFX: unlocks interrupt status registers
         retval = ipr[idx];
-
-        if (!misspeculating())
-            regs.intrlock = false;
         break;
 
       case AlphaISA::IPR_VA_FORM: