AlphaISA::zeroRegisters(XC *xc)
{
// Insure ISA semantics
- xc->setIntReg(ZeroReg, 0);
- xc->setFloatRegDouble(ZeroReg, 0.0);
+ // (no longer very clean due to the change in setIntReg() in the
+ // cpu model. Consider changing later.)
+ xc->xc->setIntReg(ZeroReg, 0);
+ xc->xc->setFloatRegDouble(ZeroReg, 0.0);
}
void
ExecContext::ev5_trap(Fault fault)
{
+ DPRINTF(Fault, "Fault %s\n", FaultName(fault));
Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
assert(!misspeculating());
break;
case AlphaISA::IPR_VA:
- // SFX: unlocks interrupt status registers
retval = ipr[idx];
-
- if (!misspeculating())
- regs.intrlock = false;
break;
case AlphaISA::IPR_VA_FORM: