Changes to support automatic renaming of the shadow registers at decode time. This...

[gem5.git] / arch / alpha / ev5.hh

diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index a5a76b5bdd27c6f73cea9398c7b806b07a5eda93..7c8465cfbb3fd9cdd5750b6d013f308852e662a9 100644 (file)
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -29,9 +29,15 @@
 #ifndef __ARCH_ALPHA_EV5_HH__
 #define __ARCH_ALPHA_EV5_HH__
 
+#include "config/alpha_tlaser.hh"
+#include "arch/alpha/isa_traits.hh"
+
 namespace EV5 {
 
-#ifdef ALPHA_TLASER
+//It seems like a safe assumption EV5 only applies to alpha
+using namespace AlphaISA;
+
+#if ALPHA_TLASER
 const uint64_t AsnMask = ULL(0x7f);
 #else
 const uint64_t AsnMask = ULL(0xff);
@@ -46,7 +52,7 @@ inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
 
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
 const int PAddrImplBits = 40;
 #else
@@ -60,7 +66,7 @@ const Addr PAddrUncachedBit43 = ULL(0x80000000000);
 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
 inline Addr Phys2K0Seg(Addr addr)
 {
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
     if (addr & PAddrUncachedBit43) {
         addr &= PAddrUncachedMask;
         addr |= PAddrUncachedBit40;