First steps toward getting full system to work with

[gem5.git] / arch / alpha / isa / main.isa

diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index 42fb294040a857c9d40847818bd3e1fb5be4e7d3..03a8e1ff51684ab3a1a981cfc826e0bbc3332108 100644 (file)
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -34,7 +34,7 @@ output header {{
 #include "config/ss_compatible_fp.hh"
 #include "cpu/static_inst.hh"
 #include "arch/alpha/faults.hh"
-#include "mem/mem_req.hh"  // some constructors use MemReq flags
+#include "mem/request.hh"  // some constructors use MemReq flags
 }};
 
 output decoder {{
@@ -45,6 +45,8 @@ output decoder {{
 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
 
 #include <math.h>
+
+using namespace AlphaISA;
 }};
 
 output exec {{
@@ -58,6 +60,9 @@ output exec {{
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
+#include "mem/packet_impl.hh"
+
+using namespace AlphaISA;
 }};
 
 ////////////////////////////////////////////////////////////////////
@@ -75,6 +80,7 @@ namespace AlphaISA;
 //
 
 // Universal (format-independent) fields
+def bitfield PALMODE    <32:32>;
 def bitfield OPCODE    <31:26>;
 def bitfield RA                <25:21>;
 def bitfield RB                <20:16>;
@@ -149,16 +155,19 @@ def operands {{
     # Int regs default to unsigned, but code should not count on this.
     # For clarity, descriptions that depend on unsigned behavior should
     # explicitly specify '.uq'.
-    'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
-    'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
-    'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
+    'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
+           'IsInteger', 1),
+    'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
+           'IsInteger', 2),
+    'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
+           'IsInteger', 3),
     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
-    'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
-    'FPCR':  (' ControlReg', 'uq', 'Fpcr', None, 1),
+    'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
+    'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),
@@ -179,7 +188,7 @@ output header {{
     /**
      * Base class for all Alpha static instructions.
      */
-    class AlphaStaticInst : public StaticInst<AlphaISA>
+    class AlphaStaticInst : public StaticInst
     {
       protected:
 
@@ -190,13 +199,15 @@ output header {{
             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
             Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
             Uniq_DepTag = AlphaISA::Uniq_DepTag,
+            Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
+            Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
             IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
         };
 
         /// Constructor.
-        AlphaStaticInst(const char *mnem, MachInst _machInst,
+        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
                         OpClass __opClass)
-            : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
+            : StaticInst(mnem, _machInst, __opClass)
         {
         }
 
@@ -254,7 +265,7 @@ output decoder {{
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
-    Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
 // Basic instruction class declaration template.
@@ -266,7 +277,7 @@ def template BasicDeclare {{
     {
       public:
         /// Constructor.
-        %(class_name)s(MachInst machInst);
+        %(class_name)s(ExtMachInst machInst);
 
         %(BasicExecDeclare)s
     };
@@ -274,7 +285,7 @@ def template BasicDeclare {{
 
 // Basic instruction class constructor template.
 def template BasicConstructor {{
-    inline %(class_name)s::%(class_name)s(MachInst machInst)
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
         %(constructor)s;
@@ -283,10 +294,10 @@ def template BasicConstructor {{
 
 // Basic instruction class execute method template.
 def template BasicExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -338,7 +349,7 @@ output header {{
 
       public:
         /// Constructor
-        Nop(const std::string _originalDisassembly, MachInst _machInst)
+        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
             : AlphaStaticInst("nop", _machInst, No_OpClass),
               originalDisassembly(_originalDisassembly)
         {
@@ -352,6 +363,17 @@ output header {{
 
         %(BasicExecDeclare)s
     };
+
+    /// Helper function for decoding nops.  Substitute Nop object
+    /// for original inst passed in as arg (and delete latter).
+    static inline
+    AlphaStaticInst *
+    makeNop(AlphaStaticInst *inst)
+    {
+        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        delete inst;
+        return nop;
+    }
 }};
 
 output decoder {{
@@ -364,21 +386,10 @@ output decoder {{
         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 #endif
     }
-
-    /// Helper function for decoding nops.  Substitute Nop object
-    /// for original inst passed in as arg (and delete latter).
-    inline
-    AlphaStaticInst *
-    makeNop(AlphaStaticInst *inst)
-    {
-        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
-        delete inst;
-        return nop;
-    }
 }};
 
 output exec {{
-    Fault *
+    Fault
     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
         return NoFault;
@@ -408,28 +419,31 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
 }};
 
 // Integer instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/int.isa"
+##include "int.isa"
 
 // Floating-point instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/fp.isa"
+##include "fp.isa"
 
 // Memory instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/mem.isa"
+##include "mem.isa"
 
 // Branch/jump instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/branch.isa"
+##include "branch.isa"
 
 // PAL instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/pal.isa"
+##include "pal.isa"
+
+// Opcdec fault instruction templates, formats, etc.
+##include "opcdec.isa"
 
 // Unimplemented instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/unimp.isa"
+##include "unimp.isa"
 
 // Unknown instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/unknown.isa"
+##include "unknown.isa"
 
 // Execution utility functions
-##include "m5/arch/alpha/isa/util.isa"
+##include "util.isa"
 
 // The actual decoder
-##include "m5/arch/alpha/isa/decoder.isa"
+##include "decoder.isa"