Copy implementations

[gem5.git] / arch / alpha / isa_desc

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 75b2f4138ccd5d082bd1ddf63e2000d198d5a5c7..41f7388e08bab8006e1c8a0f2f009431c3691156 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1000,10 +1000,50 @@ def template PrefetchDeclare {{
      */
     class %(class_name)s : public %(base_class)s
     {
+      protected:
+
+       /**
+        * "Fake" effective address computation class for "%(mnemonic)s".
+        */
+       class EAComp : public EACompBase
+       {
+         public:
+           /// Constructor
+           EAComp(MachInst machInst)
+               : EACompBase(machInst)
+           {
+               %(ea_constructor)s;
+           }
+       };
+
+       /**
+        * "Fake" memory access instruction class for "%(mnemonic)s".
+        */
+       class MemAcc : public MemAccBase
+       {
+         public:
+           /// Constructor
+           MemAcc(MachInst machInst)
+               : MemAccBase(machInst, %(op_class)s)
+           {
+               %(memacc_constructor)s;
+           }
+       };
+
+       /// Pointer to EAComp object.
+       StaticInstPtr<AlphaISA> eaCompPtr;
+       /// Pointer to MemAcc object.
+       StaticInstPtr<AlphaISA> memAccPtr;
+
       public:
+
+       StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
+       StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
+
        /// Constructor
        %(class_name)s(MachInst machInst)
-            : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+            : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
+              eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
        {
            %(constructor)s;
        }
@@ -1814,6 +1854,9 @@ decode OPCODE default Unknown::unknown() {
        0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
        0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
        0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
+       0x20: copy_load({{EA = Ra;}}, 
+                       {{fault = memAccessObj->copySrcTranslate(EA);}},
+                       IsMemRef, IsLoad, IsCopy);
     }
 
     format LoadOrPrefetch {
@@ -1833,6 +1876,9 @@ decode OPCODE default Unknown::unknown() {
        0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
        0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
        0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
+       0x24: copy_store({{EA = Rb;}},
+                        {{fault =memAccessObj->copy(EA);}},
+                        IsMemRef, IsStore, IsCopy);
     }
 
     format StoreCond {