# and memory access flags (handled here).
# Would be nice to autogenerate this list, but oh well.
- valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
+ valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
inst_flags = []
mem_flags = []
for f in flags:
# Declare the prefetch instruction object.
# convert flags from tuple to list to make them mutable
- pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp']
+ pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
0x20: copy_load({{EA = Ra;}},
- {{ fault = xc->copySrcTranslate(EA);}},
+ {{fault = xc->copySrcTranslate(EA);}},
IsMemRef, IsLoad, IsCopy);
}
0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
0x24: copy_store({{EA = Rb;}},
- {{ fault = xc->copy(EA);}},
+ {{fault = xc->copy(EA);}},
IsMemRef, IsStore, IsCopy);
}
0x1c: decode INTFUNC {
0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
- 0x32: ctlz({{
- uint64_t count = 0;
- uint64_t temp = Rb;
- if (temp & ULL(0xffffffff00000000))
- temp >>= 32;
- else
- count += 32;
- if (temp & ULL(0xffff0000))
- temp >>= 16;
- else
- count += 16;
- if (temp & ULL(0xff00))
- temp >>= 8;
- else
- count += 8;
- if (temp & ULL(0xf0))
- temp >>= 4;
- else
- count += 4;
- if (temp & ULL(0xC))
- temp >>= 2;
- else
- count += 2;
- if (temp & ULL(0x2))
- temp >>= 1;
- else
- count += 1;
- if ((temp & ULL(0x1)) != 0x1)
- count += 1;
- Rc = count;
- }}, IntAluOp);
+ 0x32: ctlz({{
+ uint64_t count = 0;
+ uint64_t temp = Rb;
+ if (temp<63:32>) temp >>= 32; else count += 32;
+ if (temp<31:16>) temp >>= 16; else count += 16;
+ if (temp<15:8>) temp >>= 8; else count += 8;
+ if (temp<7:4>) temp >>= 4; else count += 4;
+ if (temp<3:2>) temp >>= 2; else count += 2;
+ if (temp<1:1>) temp >>= 1; else count += 1;
+ if ((temp<0:0>) != 0x1) count += 1;
+ Rc = count;
+ }}, IntAluOp);
- 0x33: cttz({{
- uint64_t count = 0;
- uint64_t temp = Rb;
- if (!(temp & ULL(0x00000000ffffffff))) {
- temp >>= 32;
- count += 32;
- }
- if (!(temp & ULL(0x0000ffff))) {
- temp >>= 16;
- count += 16;
- }
- if (!(temp & ULL(0x00ff))) {
- temp >>= 8;
- count += 8;
- }
- if (!(temp & ULL(0x0f))) {
- temp >>= 4;
- count += 4;
- }
- if (!(temp & ULL(0x3))) {
- temp >>= 2;
- count += 2;
- }
- if (!(temp & ULL(0x1)))
- count += 1;
- Rc = count;
- }}, IntAluOp);
+ 0x33: cttz({{
+ uint64_t count = 0;
+ uint64_t temp = Rb;
+ if (!(temp<31:0>)) { temp >>= 32; count += 32; }
+ if (!(temp<15:0>)) { temp >>= 16; count += 16; }
+ if (!(temp<7:0>)) { temp >>= 8; count += 8; }
+ if (!(temp<3:0>)) { temp >>= 4; count += 4; }
+ if (!(temp<1:0>)) { temp >>= 2; count += 2; }
+ if (!(temp<0:0> & ULL(0x1))) count += 1;
+ Rc = count;
+ }}, IntAluOp);
format FailUnimpl {
0x30: ctpop();
}
format MiscPrefetch {
- 0xf800: wh64({{ EA = Rb; }},
- {{ xc->writeHint(EA, 64); }},
- IsMemRef, IsStore, MemWriteOp);
+ 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
+ {{ xc->writeHint(EA, 64, memAccessFlags); }},
+ IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
+ NO_FAULT);
}
format BasicOperate {
0xc000: rpcc({{
#ifdef FULL_SYSTEM
- Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
+ /* Rb is a fake dependency so here is a fun way to get
+ * the parser to understand that.
+ */
+ Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
+
#else
Ra = curTick;
#endif
0x43: m5checkpoint({{
AlphaPseudo::m5checkpoint(xc->xcBase());
}}, IsNonSpeculative);
+ 0x50: m5readfile({{
+ AlphaPseudo::readfile(xc->xcBase());
+ }}, IsNonSpeculative);
+ 0x51: m5break({{
+ AlphaPseudo::debugbreak(xc->xcBase());
+ }}, IsNonSpeculative);
+ 0x52: m5switchcpu({{
+ AlphaPseudo::switchcpu(xc->xcBase());
+ }}, IsNonSpeculative);
+
}
}