- Clean up and factor out all of the binning code into a

[gem5.git] / arch / alpha / isa_desc

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 9fee124850db346e94c35b67f25b8ff3844dab86..d6b99a8ae191ea5f8f6345318927a13bf81c9698 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1023,7 +1023,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
     # and memory access flags (handled here).
 
     # Would be nice to autogenerate this list, but oh well.
-    valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
+    valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
     inst_flags = []
     mem_flags = []
     for f in flags:
@@ -1072,7 +1072,7 @@ def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
     # Declare the prefetch instruction object.
 
     # convert flags from tuple to list to make them mutable
-    pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp']
+    pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
 
     (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
        LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
@@ -2119,12 +2119,34 @@ decode OPCODE default Unknown::unknown() {
        0x1c: decode INTFUNC {
            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
+        0x32: ctlz({{
+            uint64_t count = 0;
+            uint64_t temp = Rb;
+            if (temp<63:32>) temp >>= 32; else count += 32;
+            if (temp<31:16>) temp >>= 16; else count += 16;
+            if (temp<15:8>) temp >>= 8; else count += 8;
+            if (temp<7:4>) temp >>= 4; else count += 4;
+            if (temp<3:2>) temp >>= 2; else count += 2;
+            if (temp<1:1>) temp >>= 1; else count += 1;
+            if ((temp<0:0>) != 0x1) count += 1; 
+            Rc = count; 
+            }}, IntAluOp);
+         
+        0x33: cttz({{
+            uint64_t count = 0;
+            uint64_t temp = Rb;
+            if (!(temp<31:0>)) { temp >>= 32; count += 32; }
+            if (!(temp<15:0>)) { temp >>= 16; count += 16; }
+            if (!(temp<7:0>)) { temp >>= 8; count += 8; }
+            if (!(temp<3:0>)) { temp >>= 4; count += 4; }
+            if (!(temp<1:0>)) { temp >>= 2; count += 2; }
+            if (!(temp<0:0> & ULL(0x1))) count += 1; 
+            Rc = count; 
+        }}, IntAluOp);
 
            format FailUnimpl {
                0x30: ctpop();
                0x31: perr();
-               0x32: ctlz();
-               0x33: cttz();
                0x34: unpkbw();
                0x35: unpkbl();
                0x36: pkwb();
@@ -2369,15 +2391,20 @@ decode OPCODE default Unknown::unknown() {
        }
 
        format MiscPrefetch {
-           0xf800: wh64({{ EA = Rb; }},
-                        {{ xc->writeHint(EA, 64); }},
-                        IsMemRef, IsStore, MemWriteOp);
+           0xf800: wh64({{ EA = Rb & ~ULL(63); }},
+                        {{ xc->writeHint(EA, 64, memAccessFlags); }},
+                        IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
+                        NO_FAULT);
        }
 
        format BasicOperate {
            0xc000: rpcc({{
 #ifdef FULL_SYSTEM
-               Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
+        /* Rb is a fake dependency so here is a fun way to get
+         * the parser to understand that.
+         */
+               Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
+        
 #else
                Ra = curTick;
 #endif
@@ -2517,6 +2544,16 @@ decode OPCODE default Unknown::unknown() {
             0x43: m5checkpoint({{
                AlphaPseudo::m5checkpoint(xc->xcBase());
            }}, IsNonSpeculative);
+            0x50: m5readfile({{
+               AlphaPseudo::readfile(xc->xcBase());
+           }}, IsNonSpeculative);
+            0x51: m5break({{
+        AlphaPseudo::debugbreak(xc->xcBase());
+        }}, IsNonSpeculative);
+            0x52: m5switchcpu({{
+        AlphaPseudo::switchcpu(xc->xcBase());
+        }}, IsNonSpeculative);
+
        }
     }