Merge zizzer:/bk/m5 into zower.eecs.umich.edu:/z/hsul/bk/clean

[gem5.git] / arch / alpha / isa_desc

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index e9b93a895cd7938e05fb72cf93def1b43a84b4b5..f36413ad8bc94fa0f58a16a17aed7b3eab88c731 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1808,11 +1808,19 @@ decode OPCODE default Unknown::unknown() {
        0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
                    {{
                        uint64_t tmp = Mem_write_result;
+                       // see stq_c
                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
                    }}, LOCKED);
        0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
                    {{
                        uint64_t tmp = Mem_write_result;
+                       // If the write operation returns 0 or 1, then
+                       // this was a conventional store conditional,
+                       // and the value indicates the success/failure
+                       // of the operation.  If another value is
+                       // returned, then this was a Turbolaser
+                       // mailbox access, and we don't update the
+                       // result register at all.
                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
                    }}, LOCKED);
     }
@@ -2399,6 +2407,7 @@ decode OPCODE default Unknown::unknown() {
                if (!xc->misspeculating())
                    m5_exit();
            }}, No_OpClass);
+            0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
        }
     }