#include "targetarch/faults.hh"
#include "base/misc.hh"
-class CPU;
-class IniFile;
+class FullCPU;
+class Checkpoint;
#define TARGET_ALPHA
#endif // FULL_SYSTEM
// Are these architectural, or just for convenience?
uint8_t opcode, ra; // current instruction details (for intr's)
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
};
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
ITOUCH_ANNOTE = 0xffffffff,
};
-#if 0
- static inline Addr
- extractInstructionPrefetchTarget(const MachInst &IR, Addr PC) {
- return(0);
- }
-#endif
-
static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
int regnum);
#if 0
- static void serializeSpecialRegs(const Serializeable::Proxy &proxy,
+ static void serializeSpecialRegs(const Serializable::Proxy &proxy,
const RegFile ®s);
- static void unserializeSpecialRegs(IniFile &db,
+ static void unserializeSpecialRegs(const IniFile *db,
const std::string &category,
ConfigNode *node,
RegFile ®s);
const int ArgumentReg0 = TheISA::ArgumentReg0;
const int ArgumentReg1 = TheISA::ArgumentReg1;
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
#ifdef FULL_SYSTEM
typedef TheISA::InternalProcReg InternalProcReg;