first pass at merging m5 with linux

[gem5.git] / arch / alpha / isa_traits.hh

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index fbdcffbcf1d2841e7b03eee8a53b5e4210ea73a0..05ab8997812583dbd8e74ca6cd619a3c6fce2074 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -34,7 +34,7 @@
 #include "base/misc.hh"
 
 class FullCPU;
-class IniFile;
+class Checkpoint;
 
 #define TARGET_ALPHA
 
@@ -160,7 +160,7 @@ class AlphaISA
         uint8_t opcode, ra;            // current instruction details (for intr's)
 
         void serialize(std::ostream &os);
-        void unserialize(const IniFile *db, const std::string &section);
+        void unserialize(Checkpoint *cp, const std::string &section);
     };
 
     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
@@ -225,7 +225,7 @@ class AlphaISA
                                   int regnum);
 
 #if 0
-    static void serializeSpecialRegs(const Serializeable::Proxy &proxy,
+    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
                                      const RegFile &regs);
 
     static void unserializeSpecialRegs(const IniFile *db,
@@ -264,6 +264,7 @@ const int ReturnValueReg = TheISA::ReturnValueReg;
 const int ArgumentReg0 = TheISA::ArgumentReg0;
 const int ArgumentReg1 = TheISA::ArgumentReg1;
 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
 
 #ifdef FULL_SYSTEM
 typedef TheISA::InternalProcReg InternalProcReg;