- Clean up and factor out all of the binning code into a

[gem5.git] / arch / alpha / isa_traits.hh

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 6b78722ad4d0d146862cc62aec4171a059503c56..6559368e46ba59227dde5e98c34c929c26b7fb3f 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,9 @@
 #include "targetarch/faults.hh"
 #include "base/misc.hh"
 
+class FastCPU;
 class FullCPU;
-class IniFile;
+class Checkpoint;
 
 #define TARGET_ALPHA
 
@@ -152,12 +153,12 @@ class AlphaISA
 #ifdef FULL_SYSTEM
         IntReg palregs[NumIntRegs];    // PAL shadow registers
         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
-        int intrlock;                  // interrupt register lock flag
         int intrflag;                  // interrupt flag
         bool pal_shadow;               // using pal_shadow registers
 #endif // FULL_SYSTEM
-        // Are these architectural, or just for convenience?
-        uint8_t opcode, ra;            // current instruction details (for intr's)
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
     };
 
     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
@@ -168,13 +169,6 @@ class AlphaISA
         ITOUCH_ANNOTE = 0xffffffff,
     };
 
-#if 0
-    static inline Addr
-    extractInstructionPrefetchTarget(const MachInst &IR, Addr PC) {
-        return(0);
-    }
-#endif
-
     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
         panic("register classification not implemented");
         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
@@ -229,14 +223,21 @@ class AlphaISA
                                   int regnum);
 
 #if 0
-    static void serializeSpecialRegs(const Serializeable::Proxy &proxy,
+    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
                                      const RegFile &regs);
 
-    static void unserializeSpecialRegs(IniFile &db,
+    static void unserializeSpecialRegs(const IniFile *db,
                                        const std::string &category,
                                        ConfigNode *node,
                                        RegFile &regs);
 #endif
+
+    /**
+     * Function to insure ISA semantics about 0 registers.
+     * @param xc The execution context.
+     */
+    template <class XC>
+    static void zeroRegisters(XC *xc);
 };
 
 
@@ -268,6 +269,7 @@ const int ReturnValueReg = TheISA::ReturnValueReg;
 const int ArgumentReg0 = TheISA::ArgumentReg0;
 const int ArgumentReg1 = TheISA::ArgumentReg1;
 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
 
 #ifdef FULL_SYSTEM
 typedef TheISA::InternalProcReg InternalProcReg;