Remove intr_post function. No longer being used.

[gem5.git] / arch / alpha / isa_traits.hh

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 2da37b2e01a43a9e90df0e844a3a8defee32d542..b1980b4b68dde2107086fa67765860db05a6bb84 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -38,6 +38,7 @@ using namespace LittleEndianGuest;
 #include "sim/host.hh"
 #include "sim/faults.hh"
 
+class ExecContext;
 class FastCPU;
 class FullCPU;
 class Checkpoint;
@@ -56,15 +57,18 @@ namespace AlphaISA
 {
 
     typedef uint32_t MachInst;
-    typedef uint64_t Addr;
+    typedef uint64_t ExtMachInst;
+//    typedef uint64_t Addr;
     typedef uint8_t  RegIndex;
 
     enum {
         MemoryEnd = 0xffffffffffffffffULL,
 
-        NumIntRegs = 32,
-        NumFloatRegs = 32,
-        NumMiscRegs = 32,
+        NumIntArchRegs = 32,
+        NumPALShadowRegs = 8,
+        NumFloatArchRegs = 32,
+        // @todo: Figure out what this number really should be.
+        NumMiscArchRegs = 32,
 
         MaxRegsOfAnyType = 32,
         // Static instruction parameters
@@ -98,15 +102,23 @@ namespace AlphaISA
         DepNA = 0,
     };
 
+    enum {
+        NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
+        NumFloatRegs = NumFloatArchRegs,
+        NumMiscRegs = NumMiscArchRegs
+    };
+
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
         // 0..31 are the integer regs 0..31
         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-        FP_Base_DepTag = 32,
-        Ctrl_Base_DepTag = 64,
-        Fpcr_DepTag = 64,              // floating point control register
-        Uniq_DepTag = 65,
-        IPR_Base_DepTag = 66
+        FP_Base_DepTag = 40,
+        Ctrl_Base_DepTag = 72,
+        Fpcr_DepTag = 72,              // floating point control register
+        Uniq_DepTag = 73,
+        Lock_Flag_DepTag = 74,
+        Lock_Addr_DepTag = 75,
+        IPR_Base_DepTag = 76
     };
 
     typedef uint64_t IntReg;
@@ -123,20 +135,14 @@ namespace AlphaISA
         double d[NumFloatRegs];                // double-precision floating point view
     } FloatRegFile;
 
-    // control register file contents
-    typedef uint64_t MiscReg;
-    typedef struct {
-        uint64_t       fpcr;           // floating point condition codes
-        uint64_t       uniq;           // process-unique register
-        bool           lock_flag;      // lock flag for LL/SC
-        Addr           lock_addr;      // lock address for LL/SC
-    } MiscRegFile;
-
 extern const Addr PageShift;
 extern const Addr PageBytes;
 extern const Addr PageMask;
 extern const Addr PageOffset;
 
+// redirected register map, really only used for the full system case.
+extern const int reg_redir[NumIntRegs];
+
 #if FULL_SYSTEM
 
     typedef uint64_t InternalProcReg;
@@ -149,6 +155,39 @@ extern const Addr PageOffset;
     };
 #endif
 
+    // control register file contents
+    typedef uint64_t MiscReg;
+    class MiscRegFile {
+      protected:
+        uint64_t       fpcr;           // floating point condition codes
+        uint64_t       uniq;           // process-unique register
+        bool           lock_flag;      // lock flag for LL/SC
+        Addr           lock_addr;      // lock address for LL/SC
+
+      public:
+        MiscReg readReg(int misc_reg);
+
+        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
+
+        Fault setReg(int misc_reg, const MiscReg &val);
+
+        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+                               ExecContext *xc);
+
+#if FULL_SYSTEM
+        void clearIprs();
+
+      protected:
+        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+
+      private:
+        MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
+
+        Fault setIpr(int idx, uint64_t val, ExecContext *xc);
+#endif
+        friend class RegFile;
+    };
+
     enum {
         TotalNumRegs =
         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
@@ -171,22 +210,23 @@ extern const Addr PageOffset;
         Addr pc;                       // program counter
         Addr npc;                      // next-cycle program counter
 #if FULL_SYSTEM
-        IntReg palregs[NumIntRegs];    // PAL shadow registers
-        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
         int intrflag;                  // interrupt flag
-        bool pal_shadow;               // using pal_shadow registers
-        inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
-        inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
+        inline int instAsid()
+        { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
+        inline int dataAsid()
+        { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
 #endif // FULL_SYSTEM
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    StaticInstPtr decodeInst(MachInst);
+    static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
+
+    StaticInstPtr decodeInst(ExtMachInst);
 
     // return a no-op instruction... used for instruction fetch faults
-    extern const MachInst NoopMachInst;
+    extern const ExtMachInst NoopMachInst;
 
     enum annotes {
         ANNOTE_NONE = 0,
@@ -333,6 +373,18 @@ class SyscallReturn {
 
 #endif
 
+static inline AlphaISA::ExtMachInst
+AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
+#if FULL_SYSTEM
+    AlphaISA::ExtMachInst ext_inst = inst;
+    if (pc && 0x1)
+        return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
+    else
+        return ext_inst;
+#else
+    return AlphaISA::ExtMachInst(inst);
+#endif
+}
 
 #if FULL_SYSTEM
 //typedef TheISA::InternalProcReg InternalProcReg;