Don't use magic numbers.

[gem5.git] / arch / alpha / isa_traits.hh

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 406ffb6f3c95bb893a4d346c581836de914a08e7..b22b2fa298c8414daf6e58eef8669ecfdefe6530 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,10 +29,11 @@
 #ifndef __ISA_TRAITS_HH__
 #define __ISA_TRAITS_HH__
 
-#include "sim/host.hh"
-#include "targetarch/faults.hh"
+#include "arch/alpha/faults.hh"
 #include "base/misc.hh"
+#include "sim/host.hh"
 
+class FastCPU;
 class FullCPU;
 class Checkpoint;
 
@@ -120,11 +121,16 @@ class AlphaISA
         Addr           lock_addr;      // lock address for LL/SC
     } MiscRegFile;
 
+static const Addr PageShift = 13;
+static const Addr PageBytes = ULL(1) << PageShift;
+static const Addr PageMask = ~(PageBytes - 1);
+static const Addr PageOffset = PageBytes - 1;
+
 #ifdef FULL_SYSTEM
 
     typedef uint64_t InternalProcReg;
 
-#include "targetarch/isa_fullsys_traits.hh"
+#include "arch/alpha/isa_fullsys_traits.hh"
 
 #else
     enum {
@@ -152,12 +158,9 @@ class AlphaISA
 #ifdef FULL_SYSTEM
         IntReg palregs[NumIntRegs];    // PAL shadow registers
         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
-        int intrlock;                  // interrupt register lock flag
         int intrflag;                  // interrupt flag
         bool pal_shadow;               // using pal_shadow registers
 #endif // FULL_SYSTEM
-        // Are these architectural, or just for convenience?
-        uint8_t opcode, ra;            // current instruction details (for intr's)
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
@@ -225,7 +228,7 @@ class AlphaISA
                                   int regnum);
 
 #if 0
-    static void serializeSpecialRegs(const Serializeable::Proxy &proxy,
+    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
                                      const RegFile &regs);
 
     static void unserializeSpecialRegs(const IniFile *db,
@@ -233,6 +236,13 @@ class AlphaISA
                                        ConfigNode *node,
                                        RegFile &regs);
 #endif
+
+    /**
+     * Function to insure ISA semantics about 0 registers.
+     * @param xc The execution context.
+     */
+    template <class XC>
+    static void zeroRegisters(XC *xc);
 };
 
 
@@ -264,6 +274,7 @@ const int ReturnValueReg = TheISA::ReturnValueReg;
 const int ArgumentReg0 = TheISA::ArgumentReg0;
 const int ArgumentReg1 = TheISA::ArgumentReg1;
 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
 
 #ifdef FULL_SYSTEM
 typedef TheISA::InternalProcReg InternalProcReg;
@@ -272,7 +283,7 @@ const int NumInterruptLevels = TheISA::NumInterruptLevels;
 
 // more stuff that should be imported here, but I'm too tired to do it
 // right now...
-#include "targetarch/ev5.hh"
+#include "arch/alpha/ev5.hh"
 #endif
 
 #endif // __ALPHA_ISA_H__