Merge zizzer.eecs.umich.edu:/bk/m5/

[gem5.git] / arch / alpha / isa_traits.hh

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index d775056517888c370da516c843e7385f73511759..ff3da1502ad89f340f0c8a1de2140d46ecddc4ca 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,21 +26,27 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ISA_TRAITS_HH__
-#define __ISA_TRAITS_HH__
+#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
+#define __ARCH_ALPHA_ISA_TRAITS_HH__
 
-#include "host.hh"
-#include "faults.hh"
-#include "misc.hh"
+#include "arch/alpha/faults.hh"
+#include "base/misc.hh"
+#include "sim/host.hh"
 
-class CPU;
-class IniFile;
+class FastCPU;
+class FullCPU;
+class Checkpoint;
 
 #define TARGET_ALPHA
 
 template <class ISA> class StaticInst;
 template <class ISA> class StaticInstPtr;
 
+namespace EV5 {
+int DTB_ASN_ASN(uint64_t reg);
+int ITB_ASN_ASN(uint64_t reg);
+}
+
 class AlphaISA
 {
   public:
@@ -120,11 +126,16 @@ class AlphaISA
         Addr           lock_addr;      // lock address for LL/SC
     } MiscRegFile;
 
+static const Addr PageShift = 13;
+static const Addr PageBytes = ULL(1) << PageShift;
+static const Addr PageMask = ~(PageBytes - 1);
+static const Addr PageOffset = PageBytes - 1;
+
 #ifdef FULL_SYSTEM
 
     typedef uint64_t InternalProcReg;
 
-#include "isa_fullsys_traits.hh"
+#include "arch/alpha/isa_fullsys_traits.hh"
 
 #else
     enum {
@@ -152,12 +163,14 @@ class AlphaISA
 #ifdef FULL_SYSTEM
         IntReg palregs[NumIntRegs];    // PAL shadow registers
         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
-        int intrlock;                  // interrupt register lock flag
         int intrflag;                  // interrupt flag
         bool pal_shadow;               // using pal_shadow registers
+        inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
+        inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
 #endif // FULL_SYSTEM
-        // Are these architectural, or just for convenience?
-        uint8_t opcode, ra;            // current instruction details (for intr's)
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
     };
 
     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
@@ -168,13 +181,6 @@ class AlphaISA
         ITOUCH_ANNOTE = 0xffffffff,
     };
 
-#if 0
-    static inline Addr
-    extractInstructionPrefetchTarget(const MachInst &IR, Addr PC) {
-        return(0);
-    }
-#endif
-
     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
         panic("register classification not implemented");
         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
@@ -229,14 +235,21 @@ class AlphaISA
                                   int regnum);
 
 #if 0
-    static void serializeSpecialRegs(const Serializeable::Proxy &proxy,
+    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
                                      const RegFile &regs);
 
-    static void unserializeSpecialRegs(IniFile &db,
+    static void unserializeSpecialRegs(const IniFile *db,
                                        const std::string &category,
                                        ConfigNode *node,
                                        RegFile &regs);
 #endif
+
+    /**
+     * Function to insure ISA semantics about 0 registers.
+     * @param xc The execution context.
+     */
+    template <class XC>
+    static void zeroRegisters(XC *xc);
 };
 
 
@@ -268,15 +281,14 @@ const int ReturnValueReg = TheISA::ReturnValueReg;
 const int ArgumentReg0 = TheISA::ArgumentReg0;
 const int ArgumentReg1 = TheISA::ArgumentReg1;
 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
 
 #ifdef FULL_SYSTEM
 typedef TheISA::InternalProcReg InternalProcReg;
 const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 const int NumInterruptLevels = TheISA::NumInterruptLevels;
 
-// more stuff that should be imported here, but I'm too tired to do it
-// right now...
-#include "ev5.hh"
+#include "arch/alpha/ev5.hh"
 #endif
 
-#endif // __ALPHA_ISA_H__
+#endif // __ARCH_ALPHA_ISA_TRAITS_HH__