#include "arch/alpha/pseudo_inst.hh"
#include "arch/alpha/vtophys.hh"
#include "cpu/base_cpu.hh"
+#include "cpu/sampling_cpu/sampling_cpu.hh"
#include "cpu/exec_context.hh"
+#include "kern/kernel_stats.hh"
#include "sim/param.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/stat_control.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
+#include "sim/debug.hh"
using namespace std;
+
+extern SamplingCPU *SampCPU;
+
using namespace Stats;
namespace AlphaPseudo
void
arm(ExecContext *xc)
{
- xc->kernelStats.arm();
+ xc->kernelStats->arm();
}
void
return;
xc->suspend();
- xc->kernelStats.quiesce();
+ xc->kernelStats->quiesce();
}
void
ivlb(ExecContext *xc)
{
- xc->kernelStats.ivlb();
+ xc->kernelStats->ivlb();
}
void
void
readfile(ExecContext *xc)
{
- const string &file = xc->cpu->system->readfile;
+ const string &file = xc->cpu->system->params->readfile;
if (file.empty()) {
xc->regs.intRegFile[0] = ULL(0);
return;
void checkParams();
};
- Context context("PseudoInsts");
+ Context context("pseudo_inst");
Param<bool> __quiesce(&context, "quiesce",
"enable quiesce instructions",
doStatisticsInsts = __statistics;
doCheckpointInsts = __checkpoint;
}
+
+ void debugbreak(ExecContext *xc)
+ {
+ debug_break();
+ }
+
+ void switchcpu(ExecContext *xc)
+ {
+ if (SampCPU)
+ SampCPU->switchCPUs();
+ }
}