/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <string>
-#include "pmap.h"
-
-#include "exec_context.hh"
-#include "physical_memory.hh"
-#include "trace.hh"
-#include "vtophys.hh"
+#include "arch/alpha/vtophys.hh"
+#include "base/trace.hh"
+#include "cpu/exec_context.hh"
+#include "mem/functional/physical.hh"
using namespace std;
+using namespace AlphaISA;
-inline Addr
-level3_index(Addr vaddr)
-{ return (vaddr >> ALPHA_PGSHIFT) & PTEMASK; }
-
-inline Addr
-level2_index(Addr vaddr)
-{ return (vaddr >> (ALPHA_PGSHIFT + NPTEPG_SHIFT)) & PTEMASK; }
-
-inline Addr
-level1_index(Addr vaddr)
-{ return (vaddr >> (ALPHA_PGSHIFT + 2 * NPTEPG_SHIFT)) & PTEMASK; }
-
-Addr
-kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, Addr vaddr)
+AlphaISA::PageTableEntry
+kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
{
- uint64_t level1_map = ptbr;
- Addr level1_pte = level1_map + (level1_index(vaddr) << PTESHIFT);
-
- uint64_t level1 = pmem->phys_read_qword(level1_pte);
- if (!entry_valid(level1)) {
+ Addr level1_pte = ptbr + vaddr.level1();
+ AlphaISA::PageTableEntry level1 = pmem->phys_read_qword(level1_pte);
+ if (!level1.valid()) {
DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
return 0;
}
- uint64_t level2_map = PMAP_PTE_PA(level1);
- Addr level2_pte = level2_map + (level2_index(vaddr) << PTESHIFT);
- uint64_t level2 = pmem->phys_read_qword(level2_pte);
- if (!entry_valid(level2)) {
+ Addr level2_pte = level1.paddr() + vaddr.level2();
+ AlphaISA::PageTableEntry level2 = pmem->phys_read_qword(level2_pte);
+ if (!level2.valid()) {
DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
return 0;
}
- uint64_t level3_map = PMAP_PTE_PA(level2);
- Addr level3_pte = level3_map + (level3_index(vaddr) << PTESHIFT);
-
- return level3_pte;
+ Addr level3_pte = level2.paddr() + vaddr.level3();
+ AlphaISA::PageTableEntry level3 = pmem->phys_read_qword(level3_pte);
+ if (!level3.valid()) {
+ DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
+ return 0;
+ }
+ return level3;
}
Addr
vtophys(PhysicalMemory *xc, Addr vaddr)
{
Addr paddr = 0;
- if (vaddr < ALPHA_K0SEG_BASE)
+ if (AlphaISA::IsUSeg(vaddr))
DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (vaddr < ALPHA_K1SEG_BASE)
- paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
+ else if (AlphaISA::IsK0Seg(vaddr))
+ paddr = AlphaISA::K0Seg2Phys(vaddr);
else
panic("vtophys: ptbr is not set on virtual lookup");
}
Addr
-vtophys(ExecContext *xc, Addr vaddr)
+vtophys(ExecContext *xc, Addr addr)
{
- Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
+ AlphaISA::VAddr vaddr = addr;
+ Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
Addr paddr = 0;
- if (vaddr < ALPHA_K0SEG_BASE) {
- DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- } else if (vaddr < ALPHA_K1SEG_BASE) {
- paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
+ //@todo Andrew couldn't remember why he commented some of this code
+ //so I put it back in. Perhaps something to do with gdb debugging?
+ if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
+ paddr = vaddr & ~ULL(1);
} else {
- if (!ptbr)
- panic("vtophys: ptbr is not set on virtual lookup");
-
- Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
- uint64_t entry = xc->physmem->phys_read_qword(pte);
- if (pte && entry_valid(entry))
- paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
+ if (AlphaISA::IsK0Seg(vaddr)) {
+ paddr = AlphaISA::K0Seg2Phys(vaddr);
+ } else if (!ptbr) {
+ paddr = vaddr;
+ } else {
+ AlphaISA::PageTableEntry pte =
+ kernel_pte_lookup(xc->physmem, ptbr, vaddr);
+ if (pte.valid())
+ paddr = pte.paddr() | vaddr.offset();
+ }
}
+
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
}
+uint8_t *
+ptomem(ExecContext *xc, Addr paddr, size_t len)
+{
+ return xc->physmem->dma_addr(paddr, len);
+}
+
uint8_t *
vtomem(ExecContext *xc, Addr vaddr, size_t len)
{
Addr paddr = vtophys(xc, vaddr);
return xc->physmem->dma_addr(paddr, len);
}
+
+void
+CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
+{
+ Addr paddr;
+ char *dmaaddr;
+ char *dst = (char *)dest;
+ int len;
+
+ paddr = vtophys(xc, src);
+ len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
+ (int)cplen);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
+ assert(dmaaddr);
+
+ memcpy(dst, dmaaddr, len);
+ if (len == cplen)
+ return;
+
+ cplen -= len;
+ dst += len;
+ src += len;
+
+ while (cplen > AlphaISA::PageBytes) {
+ paddr = vtophys(xc, src);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
+ assert(dmaaddr);
+
+ memcpy(dst, dmaaddr, AlphaISA::PageBytes);
+ cplen -= AlphaISA::PageBytes;
+ dst += AlphaISA::PageBytes;
+ src += AlphaISA::PageBytes;
+ }
+
+ if (cplen > 0) {
+ paddr = vtophys(xc, src);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
+ assert(dmaaddr);
+
+ memcpy(dst, dmaaddr, cplen);
+ }
+}
+
+void
+CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
+{
+ Addr paddr;
+ char *dmaaddr;
+ char *src = (char *)source;
+ int len;
+
+ paddr = vtophys(xc, dest);
+ len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
+ (int)cplen);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
+ assert(dmaaddr);
+
+ memcpy(dmaaddr, src, len);
+ if (len == cplen)
+ return;
+
+ cplen -= len;
+ src += len;
+ dest += len;
+
+ while (cplen > AlphaISA::PageBytes) {
+ paddr = vtophys(xc, dest);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
+ assert(dmaaddr);
+
+ memcpy(dmaaddr, src, AlphaISA::PageBytes);
+ cplen -= AlphaISA::PageBytes;
+ src += AlphaISA::PageBytes;
+ dest += AlphaISA::PageBytes;
+ }
+
+ if (cplen > 0) {
+ paddr = vtophys(xc, dest);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
+ assert(dmaaddr);
+
+ memcpy(dmaaddr, src, cplen);
+ }
+}
+
+void
+CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
+{
+ Addr paddr;
+ char *dmaaddr;
+ int len;
+
+ paddr = vtophys(xc, vaddr);
+ len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
+ (int)maxlen);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
+ assert(dmaaddr);
+
+ char *term = (char *)memchr(dmaaddr, 0, len);
+ if (term)
+ len = term - dmaaddr + 1;
+
+ memcpy(dst, dmaaddr, len);
+
+ if (term || len == maxlen)
+ return;
+
+ maxlen -= len;
+ dst += len;
+ vaddr += len;
+
+ while (maxlen > AlphaISA::PageBytes) {
+ paddr = vtophys(xc, vaddr);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
+ assert(dmaaddr);
+
+ char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
+ len = term ? (term - dmaaddr + 1) : AlphaISA::PageBytes;
+
+ memcpy(dst, dmaaddr, len);
+ if (term)
+ return;
+
+ maxlen -= AlphaISA::PageBytes;
+ dst += AlphaISA::PageBytes;
+ vaddr += AlphaISA::PageBytes;
+ }
+
+ if (maxlen > 0) {
+ paddr = vtophys(xc, vaddr);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, maxlen);
+ assert(dmaaddr);
+
+ char *term = (char *)memchr(dmaaddr, 0, maxlen);
+ len = term ? (term - dmaaddr + 1) : maxlen;
+
+ memcpy(dst, dmaaddr, len);
+
+ maxlen -= len;
+ }
+
+ if (maxlen == 0)
+ dst[maxlen] = '\0';
+}
projects / gem5.git / blobdiff