Enable register windows.

[gem5.git] / arch / sparc / isa_traits.hh

diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index bbc66202c23d817ea6daa5c600e67cbe6f258e5d..57206c5e598a69cddb749d2ead3920559076889a 100644 (file)
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -123,8 +123,8 @@ namespace SparcISA
     const int SyscallPseudoReturnReg = ArgumentReg1;
 
     //XXX These numbers are bogus
-    const int MaxInstSrcRegs = 3;
-    const int MaxInstDestRegs = 2;
+    const int MaxInstSrcRegs = 8;
+    const int MaxInstDestRegs = 3;
 
     typedef uint64_t IntReg;
 
@@ -174,12 +174,12 @@ namespace SparcISA
         // and put the return value itself in the standard return value reg ().
         if (return_value.successful()) {
             // no error
-            regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0);
-            regs->intRegFile[ReturnValueReg] = return_value.value();
+            regs->setMiscReg(MISCREG_CCR_ICC_C, 0);
+            regs->setIntReg(ReturnValueReg, return_value.value());
         } else {
             // got an error, return details
-            regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1);
-            regs->intRegFile[ReturnValueReg] = -return_value.value();
+            regs->setMiscReg(MISCREG_CCR_ICC_C, 1);
+            regs->setIntReg(ReturnValueReg, return_value.value());
         }
     }
 #endif