Merge branch 'master' into clk2ff-better-names

[yosys.git] / backends / aiger / aiger.cc

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index cac32a8da28a7fe4d1c3e31648164dff90d9e1d8..35935b847e02e3489d69fb4d479dad16d79c4e35 100644 (file)
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -111,7 +111,7 @@ struct AigerWriter
 
                // promote public wires
                for (auto wire : module->wires())
-                       if (wire->name[0] == '\\')
+                       if (wire->name.isPublic())
                                sigmap.add(wire);
 
                // promote input wires
@@ -629,30 +629,30 @@ struct AigerWriter
                                int a = aig_map.at(sig[i]);
 
                                if (verbose_map)
-                                       wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
+                                       wire_lines[a] += stringf("wire %d %d %s\n", a, wire->start_offset+i, log_id(wire));
 
                                if (wire->port_input) {
                                        log_assert((a & 1) == 0);
-                                       input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+                                       input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire));
                                }
 
                                if (wire->port_output) {
                                        int o = ordered_outputs.at(sig[i]);
-                                       output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
+                                       output_lines[o] += stringf("output %d %d %s\n", o, wire->start_offset+i, log_id(wire));
                                }
 
                                if (init_inputs.count(sig[i])) {
                                        int a = init_inputs.at(sig[i]);
                                        log_assert((a & 1) == 0);
-                                       init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+                                       init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire));
                                }
 
                                if (ordered_latches.count(sig[i])) {
                                        int l = ordered_latches.at(sig[i]);
                                        if (zinit_mode && (aig_latchinit.at(l) == 1))
-                                               latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
+                                               latch_lines[l] += stringf("invlatch %d %d %s\n", l, wire->start_offset+i, log_id(wire));
                                        else
-                                               latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
+                                               latch_lines[l] += stringf("latch %d %d %s\n", l, wire->start_offset+i, log_id(wire));
                                }
                        }
                }
@@ -681,7 +681,7 @@ struct AigerWriter
 
 struct AigerBackend : public Backend {
        AigerBackend() : Backend("aiger", "write design to AIGER file") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -719,7 +719,7 @@ struct AigerBackend : public Backend {
                log("        AIGER file happy.\n");
                log("\n");
        }
-       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
        {
                bool ascii_mode = false;
                bool zinit_mode = false;