dict<SigBit, SigBit> not_map, ff_map, alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
//pool<SigBit> initstate_bits;
- vector<std::pair<SigBit,int>> ci_bits, co_bits;
+ vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
+ vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
vector<pair<int, int>> aig_gates;
vector<int> aig_latchin, aig_latchinit, aig_outputs;
}
}
if (is_output) {
+ input_bits.insert(b);
SigBit O = sigmap(b);
- input_bits.insert(O);
+ if (O != b)
+ alias_map[O] = b;
undriven_bits.erase(O);
}
}
// Fully pad all unused input connections of this box cell with S0
// Fully pad all undriven output connections of this box cell with anonymous wires
- for (const auto w : box_module->wires()) {
+ // NB: Assume box_module->ports are sorted alphabetically
+ // (as RTLIL::Module::fixup_ports() would do)
+ for (const auto &port_name : box_module->ports) {
+ RTLIL::Wire* w = box_module->wire(port_name);
+ log_assert(w);
+ auto it = cell->connections_.find(port_name);
if (w->port_input) {
- auto it = cell->connections_.find(w->name);
+ RTLIL::SigSpec rhs;
if (it != cell->connections_.end()) {
if (GetSize(it->second) < GetSize(w))
it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
+ rhs = it->second;
+ }
+ else {
+ rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
+ cell->setPort(port_name, rhs);
+ }
+
+ int offset = 0;
+ for (const auto &b : rhs.bits()) {
+ SigBit I = sigmap(b);
+ if (I != b)
+ alias_map[b] = I;
+ co_bits.emplace_back(b, cell, port_name, offset++, 0);
+ unused_bits.erase(b);
}
- else
- cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
}
if (w->port_output) {
+ RTLIL::SigSpec rhs;
auto it = cell->connections_.find(w->name);
if (it != cell->connections_.end()) {
if (GetSize(it->second) < GetSize(w))
it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
+ rhs = it->second;
}
- else
- cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w));
- }
- }
-
- // Box ordering is alphabetical
- cell->connections_.sort(RTLIL::sort_by_id_str());
- for (const auto &c : cell->connections()) {
- for (auto b : c.second.bits()) {
- auto is_input = cell->input(c.first);
- auto is_output = cell->output(c.first);
- log_assert(is_input || is_output);
- if (is_input) {
- SigBit I = sigmap(b);
- if (I != b)
- alias_map[b] = I;
- co_bits.emplace_back(b, 0);
+ else {
+ rhs = module->addWire(NEW_ID, GetSize(w));
+ cell->setPort(port_name, rhs);
}
- if (is_output) {
+
+ int offset = 0;
+ for (const auto &b : rhs.bits()) {
+ ci_bits.emplace_back(b, cell, port_name, offset++);
SigBit O = sigmap(b);
- ci_bits.emplace_back(O, 0);
+ if (O != b)
+ alias_map[O] = b;
+ undriven_bits.erase(O);
}
}
}
-
box_list.emplace_back(cell);
}
}
}
- // Do some CI/CO post-processing:
- // CIs cannot be undriven
- for (const auto &c : ci_bits)
- undriven_bits.erase(c.first);
// Erase all POs that are undriven
if (!holes_mode)
for (auto bit : undriven_bits)
}
init_map.sort();
- input_bits.sort();
- output_bits.sort();
+ if (holes_mode) {
+ struct sort_by_port_id {
+ bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
+ return a.wire->port_id < b.wire->port_id;
+ }
+ };
+ input_bits.sort(sort_by_port_id());
+ output_bits.sort(sort_by_port_id());
+ }
+ else {
+ input_bits.sort();
+ output_bits.sort();
+ }
+
not_map.sort();
ff_map.sort();
and_map.sort();
for (auto &c : ci_bits) {
aig_m++, aig_i++;
- c.second = 2*aig_m;
- aig_map[c.first] = c.second;
+ aig_map[std::get<0>(c)] = 2*aig_m;
}
if (imode && input_bits.empty()) {
// aig_latchin.push_back(1);
for (auto &c : co_bits) {
- RTLIL::SigBit bit = c.first;
- c.second = aig_o++;
- ordered_outputs[bit] = c.second;
+ RTLIL::SigBit bit = std::get<0>(c);
+ std::get<4>(c) = aig_o++;
+ ordered_outputs[bit] = std::get<4>(c);
aig_outputs.push_back(bit2aig(bit));
}
holes_module = module->design->addModule("\\__holes__");
log_assert(holes_module);
+ int port_id = 1;
+ int box_count = 0;
for (auto cell : box_list) {
RTLIL::Module* box_module = module->design->module(cell->type);
int box_inputs = 0, box_outputs = 0;
if (!holes_wire) {
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
holes_wire->port_input = true;
+ holes_wire->port_id = port_id++;
+ holes_module->ports.push_back(holes_wire->name);
}
if (holes_cell)
port_wire.append(holes_wire);
else
holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
holes_wire->port_output = true;
+ holes_wire->port_id = port_id++;
+ holes_module->ports.push_back(holes_wire->name);
if (holes_cell)
port_wire.append(holes_wire);
else
write_h_buffer(box_inputs);
write_h_buffer(box_outputs);
write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
- write_h_buffer(0 /* OldBoxNum */);
+ write_h_buffer(box_count++);
}
f << "h";
f.write(buffer_str.data(), buffer_str.size());
if (holes_module) {
- holes_module->fixup_ports();
+ // NB: fixup_ports() will sort ports by name
+ //holes_module->fixup_ports();
+ holes_module->check();
holes_module->design->selection_stack.emplace_back(false);
RTLIL::Selection& sel = holes_module->design->selection_stack.back();
if (output_bits.count(b)) {
int o = ordered_outputs.at(b);
- output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
+ output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire));
continue;
}
}
}
- for (const auto &c : ci_bits) {
- RTLIL::SigBit b = c.first;
- RTLIL::Wire *wire = b.wire;
- int i = b.offset;
- int a = bit2aig(b);
- log_assert((a & 1) == 0);
- input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
- }
-
- for (const auto &c : co_bits) {
- RTLIL::SigBit b = c.first;
- RTLIL::Wire *wire = b.wire;
- int o = c.second;
- if (wire)
- output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire));
- else
- output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data);
- }
-
input_lines.sort();
for (auto &it : input_lines)
f << it.second;
- log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
+ log_assert(input_lines.size() == input_bits.size());
init_lines.sort();
for (auto &it : init_lines)
f << it.second;
+ int box_count = 0;
+ for (auto cell : box_list)
+ f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
+
output_lines.sort();
for (auto &it : output_lines)
f << it.second;
- log_assert(output_lines.size() == output_bits.size() + co_bits.size());
+ log_assert(output_lines.size() == output_bits.size());
if (omode && output_bits.empty())
f << "output " << output_lines.size() << " 0 __dummy_o__\n";
projects / yosys.git / blobdiff