PI before CI

[yosys.git] / backends / aiger / xaiger.cc

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 2b7f52d30c765b7651b8beea9b2db04f65b986b0..b0770ec96c715ff23fedb55052356d0e075181cc 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -157,11 +157,16 @@ struct XAigerWriter
                        }
                }
 
-               for (auto bit : input_bits)
-                       undriven_bits.erase(bit);
+               for (auto bit : input_bits) {
+                       if (!bit.wire->port_output)
+                               undriven_bits.erase(bit);
+                       // Erase POs that are also PIs
+                       output_bits.erase(bit);
+               }
 
                for (auto bit : output_bits)
-                       unused_bits.erase(bit);
+                       if (!bit.wire->port_input)
+                               unused_bits.erase(bit);
 
                for (auto cell : module->cells())
                {
@@ -210,19 +215,23 @@ struct XAigerWriter
                                for (auto b : c.second.bits()) {
                                        Wire *w = b.wire;
                                        if (!w) continue;
-                                       if (cell->input(c.first)) {
+                                       auto is_input = cell->input(c.first);
+                                       auto is_output = cell->output(c.first);
+                                       log_assert(is_input || is_output);
+                                       if (is_input) {
                                                if (!w->port_input) {
                                                        SigBit I = sigmap(b);
                                                        if (I != b)
                                                                alias_map[b] = I;
-                                                       co_bits.insert(b);
+                                                       if (!output_bits.count(b))
+                                                               co_bits.insert(b);
                                                }
                                        }
-                                       else if (cell->output(c.first)) {
+                                       if (is_output) {
                                                SigBit O = sigmap(b);
-                                               ci_bits.insert(O);
+                                               if (!input_bits.count(O))
+                                                       ci_bits.insert(O);
                                        }
-                                       else log_abort();
                                }
                                if (!type_map.count(cell->type))
                                        type_map[cell->type] = type_map.size()+1;
@@ -230,22 +239,33 @@ struct XAigerWriter
                        //log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
                }
 
+               for (auto bit : input_bits) {
+                       RTLIL::Wire *wire = bit.wire;
+                       // If encountering an inout port, then create a new wire with $inout.out
+                       // suffix, make it a CO driven by the existing inout, and inherit existing
+                       // inout's drivers
+                       if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
+                               RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
+                               if (!new_wire)
+                                       new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
+                               SigBit new_bit(new_wire, bit.offset);
+                               module->connect(new_bit, bit);
+                               if (not_map.count(bit))
+                                       not_map[new_bit] = not_map.at(bit);
+                               else if (and_map.count(bit))
+                                       and_map[new_bit] = and_map.at(bit);
+                               else if (alias_map.count(bit))
+                                       alias_map[new_bit] = alias_map.at(bit);
+                               co_bits.insert(new_bit);
+                       }
+               }
+
                // Do some CI/CO post-processing:
                // Erase all POs and COs that are undriven
                for (auto bit : undriven_bits) {
                        co_bits.erase(bit);
                        output_bits.erase(bit);
                }
-               // Erase all POs and CIs that are also PIs
-               for (auto bit : input_bits) {
-                       output_bits.erase(bit);
-                       ci_bits.erase(bit);
-               }
-               for (auto bit : output_bits) {
-                       ci_bits.erase(bit);
-                       // POs override COs
-                       co_bits.erase(bit);
-               }
                // Erase all CIs that are also COs
                for (auto bit : co_bits)
                        ci_bits.erase(bit);
@@ -275,12 +295,12 @@ struct XAigerWriter
                aig_map[State::S0] = 0;
                aig_map[State::S1] = 1;
 
-               for (auto bit : ci_bits) {
+               for (auto bit : input_bits) {
                        aig_m++, aig_i++;
                        aig_map[bit] = 2*aig_m;
                }
 
-               for (auto bit : input_bits) {
+               for (auto bit : ci_bits) {
                        aig_m++, aig_i++;
                        aig_map[bit] = 2*aig_m;
                }