* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
if (bit.wire == nullptr) {
if (wire->port_output) {
aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
- //output_bits.insert(wirebit);
+ output_bits.insert(wirebit);
}
continue;
}
if (wire->port_output) {
if (bit != wirebit)
alias_map[wirebit] = bit;
- //output_bits.insert(wirebit);
+ output_bits.insert(wirebit);
}
}
}
- for (auto bit : input_bits)
- undriven_bits.erase(bit);
+ for (auto bit : input_bits) {
+ if (!bit.wire->port_output)
+ undriven_bits.erase(bit);
+ // Erase POs that are also PIs
+ output_bits.erase(bit);
+ }
for (auto bit : output_bits)
- unused_bits.erase(bit);
+ if (!bit.wire->port_input)
+ unused_bits.erase(bit);
for (auto cell : module->cells())
{
{
SigBit A = sigmap(cell->getPort("\\A").as_bit());
SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
- if (Y.wire->port_output)
- output_bits.insert(Y);
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
continue;
}
- if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
- {
- SigBit D = sigmap(cell->getPort("\\D").as_bit());
- SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
- unused_bits.erase(D);
- undriven_bits.erase(Q);
- ff_map[Q] = D;
- continue;
- }
+ //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
+ //{
+ // SigBit D = sigmap(cell->getPort("\\D").as_bit());
+ // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
+ // unused_bits.erase(D);
+ // undriven_bits.erase(Q);
+ // ff_map[Q] = D;
+ // continue;
+ //}
if (cell->type == "$_AND_")
{
SigBit A = sigmap(cell->getPort("\\A").as_bit());
SigBit B = sigmap(cell->getPort("\\B").as_bit());
SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
- if (Y.wire->port_output)
- output_bits.insert(Y);
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
for (const auto &c : cell->connections()) {
if (c.second.is_fully_const()) continue;
- SigBit b = c.second.as_bit();
- Wire *w = b.wire;
- if (cell->input(c.first)) {
- SigBit I = sigmap(b);
- if (!w->port_input)
- co_bits.insert(I);
- }
- else if (cell->output(c.first)) {
- SigBit O = sigmap(b);
- ci_bits.insert(O);
+ for (auto b : c.second.bits()) {
+ Wire *w = b.wire;
+ if (!w) continue;
+ auto is_input = cell->input(c.first);
+ auto is_output = cell->output(c.first);
+ log_assert(is_input || is_output);
+ if (is_input) {
+ if (!w->port_input) {
+ SigBit I = sigmap(b);
+ if (I != b)
+ alias_map[b] = I;
+ if (!output_bits.count(b))
+ co_bits.insert(b);
+ }
+ }
+ if (is_output) {
+ SigBit O = sigmap(b);
+ if (!input_bits.count(O))
+ ci_bits.insert(O);
+ }
}
- else log_abort();
if (!type_map.count(cell->type))
type_map[cell->type] = type_map.size()+1;
}
//log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
}
+ for (auto bit : input_bits) {
+ RTLIL::Wire *wire = bit.wire;
+ // If encountering an inout port, then create a new wire with $inout.out
+ // suffix, make it a CO driven by the existing inout, and inherit existing
+ // inout's drivers
+ if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
+ RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
+ if (!new_wire)
+ new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
+ SigBit new_bit(new_wire, bit.offset);
+ module->connect(new_bit, bit);
+ if (not_map.count(bit))
+ not_map[new_bit] = not_map.at(bit);
+ else if (and_map.count(bit))
+ and_map[new_bit] = and_map.at(bit);
+ else if (alias_map.count(bit))
+ alias_map[new_bit] = alias_map.at(bit);
+ co_bits.insert(new_bit);
+ }
+ }
+
// Do some CI/CO post-processing:
- // Erase all COs that are undriven
- for (auto bit : undriven_bits)
+ // Erase all POs and COs that are undriven
+ for (auto bit : undriven_bits) {
co_bits.erase(bit);
- // Erase all CIs that are also COs or POs
+ output_bits.erase(bit);
+ }
+ // Erase all CIs that are also COs
for (auto bit : co_bits)
ci_bits.erase(bit);
- for (auto bit : output_bits)
- ci_bits.erase(bit);
// CIs cannot be undriven
for (auto bit : ci_bits)
undriven_bits.erase(bit);
aig_map[State::S0] = 0;
aig_map[State::S1] = 1;
- for (auto bit : ci_bits) {
+ for (auto bit : input_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
- for (auto bit : input_bits) {
+ for (auto bit : ci_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
aig_outputs.push_back(bit2aig(bit));
}
- if (omode && output_bits.empty()) {
+ if (omode && output_bits.empty() && co_bits.empty()) {
aig_o++;
aig_outputs.push_back(0);
}
}
}
- void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
+ void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
{
int aig_obc = aig_o;
int aig_obcj = aig_obc;
{
dict<string, vector<string>> symbols;
+ bool output_seen = false;
for (auto wire : module->wires())
{
//if (wire->name[0] == '$')
for (int i = 0; i < GetSize(wire); i++)
{
- if (sig[i].wire == nullptr) {
- if (wire->port_output)
- sig[i] = SigBit(wire, i);
- else
- continue;
- }
-
- if (input_bits.count(sig[i]) || ci_bits.count(SigSpec(sig[i]))) {
+ RTLIL::SigBit b(wire, i);
+ if (input_bits.count(b) || ci_bits.count(b)) {
int a = aig_map.at(sig[i]);
log_assert((a & 1) == 0);
if (GetSize(wire) != 1)
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
}
- if (output_bits.count(SigSpec(wire, i)) || co_bits.count(SigSpec(wire, i))) {
- int o = ordered_outputs.at(SigSpec(wire, i));
+ if (output_bits.count(b) || co_bits.count(b)) {
+ int o = ordered_outputs.at(b);
+ output_seen = !miter_mode;
if (GetSize(wire) != 1)
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
else
}
}
+ if (omode && !output_seen)
+ symbols["o0"].push_back("__dummy_o__");
+
symbols.sort();
for (auto &sym : symbols) {
f << stringf("c\nGenerated by %s\n", yosys_version_str);
}
- void write_map(std::ostream &f, bool verbose_map)
+ void write_map(std::ostream &f, bool verbose_map, bool omode)
{
dict<int, string> input_lines;
dict<int, string> init_lines;
for (int i = 0; i < GetSize(wire); i++)
{
- if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
- continue;
-
- int a = aig_map.at(sig[i]);
-
- if (verbose_map)
- wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
-
- if (wire->port_input || ci_bits.count(RTLIL::SigBit{wire, i})) {
+ RTLIL::SigBit b(wire, i);
+ if (input_bits.count(b) || ci_bits.count(b)) {
+ int a = aig_map.at(sig[i]);
log_assert((a & 1) == 0);
input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+ continue;
}
- if (output_bits.count(RTLIL::SigBit{wire, i}) || co_bits.count(RTLIL::SigBit{wire, i})) {
- int o = ordered_outputs.at(sig[i]);
+ if (output_bits.count(b) || co_bits.count(b)) {
+ int o = ordered_outputs.at(b);
output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
+ continue;
}
if (init_inputs.count(sig[i])) {
int a = init_inputs.at(sig[i]);
log_assert((a & 1) == 0);
init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+ continue;
}
if (ordered_latches.count(sig[i])) {
latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
else
latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
+ continue;
+ }
+
+ if (verbose_map) {
+ if (aig_map.count(sig[i]) == 0)
+ continue;
+
+ int a = aig_map.at(sig[i]);
+ wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
}
}
}
input_lines.sort();
for (auto &it : input_lines)
f << it.second;
+ log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
init_lines.sort();
for (auto &it : init_lines)
output_lines.sort();
for (auto &it : output_lines)
f << it.second;
+ log_assert(output_lines.size() == output_bits.size() + co_bits.size());
+ if (omode && output_lines.empty())
+ f << "output 0 0 __dummy_o__\n";
latch_lines.sort();
for (auto &it : latch_lines)
log_error("Can't find top module in current design!\n");
XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
- writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
+ writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
if (!map_filename.empty()) {
std::ofstream mapf;
mapf.open(map_filename.c_str(), std::ofstream::trunc);
if (mapf.fail())
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
- writer.write_map(mapf, verbose_map);
+ writer.write_map(mapf, verbose_map, omode);
}
}
} XAigerBackend;
projects / yosys.git / blobdiff