* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
}
}
- for (auto bit : input_bits)
- undriven_bits.erase(bit);
+ for (auto bit : input_bits) {
+ if (!bit.wire->port_output)
+ undriven_bits.erase(bit);
+ // Erase POs that are also PIs
+ output_bits.erase(bit);
+ }
for (auto bit : output_bits)
- unused_bits.erase(bit);
+ if (!bit.wire->port_input)
+ unused_bits.erase(bit);
for (auto cell : module->cells())
{
for (auto b : c.second.bits()) {
Wire *w = b.wire;
if (!w) continue;
- if (cell->input(c.first)) {
+ auto is_input = cell->input(c.first);
+ auto is_output = cell->output(c.first);
+ log_assert(is_input || is_output);
+ if (is_input) {
if (!w->port_input) {
SigBit I = sigmap(b);
if (I != b)
alias_map[b] = I;
- co_bits.insert(b);
+ if (!output_bits.count(b))
+ co_bits.insert(b);
}
}
- else if (cell->output(c.first)) {
+ if (is_output) {
SigBit O = sigmap(b);
- ci_bits.insert(O);
+ if (!input_bits.count(O))
+ ci_bits.insert(O);
}
- else log_abort();
}
if (!type_map.count(cell->type))
type_map[cell->type] = type_map.size()+1;
//log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
}
+ for (auto bit : input_bits) {
+ RTLIL::Wire *wire = bit.wire;
+ // If encountering an inout port, then create a new wire with $inout.out
+ // suffix, make it a CO driven by the existing inout, and inherit existing
+ // inout's drivers
+ if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
+ RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
+ if (!new_wire)
+ new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
+ SigBit new_bit(new_wire, bit.offset);
+ module->connect(new_bit, bit);
+ if (not_map.count(bit))
+ not_map[new_bit] = not_map.at(bit);
+ else if (and_map.count(bit))
+ and_map[new_bit] = and_map.at(bit);
+ else if (alias_map.count(bit))
+ alias_map[new_bit] = alias_map.at(bit);
+ co_bits.insert(new_bit);
+ }
+ }
+
// Do some CI/CO post-processing:
// Erase all POs and COs that are undriven
for (auto bit : undriven_bits) {
co_bits.erase(bit);
output_bits.erase(bit);
}
- // Erase all POs and CIs that are also PIs
- for (auto bit : input_bits) {
- output_bits.erase(bit);
- ci_bits.erase(bit);
- }
- for (auto bit : output_bits) {
- ci_bits.erase(bit);
- // POs override COs
- co_bits.erase(bit);
- }
// Erase all CIs that are also COs
for (auto bit : co_bits)
ci_bits.erase(bit);
aig_map[State::S0] = 0;
aig_map[State::S1] = 1;
- for (auto bit : ci_bits) {
+ for (auto bit : input_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
- for (auto bit : input_bits) {
+ for (auto bit : ci_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
}
}
- void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
+ void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
{
int aig_obc = aig_o;
int aig_obcj = aig_obc;
{
dict<string, vector<string>> symbols;
+ bool output_seen = false;
for (auto wire : module->wires())
{
//if (wire->name[0] == '$')
for (int i = 0; i < GetSize(wire); i++)
{
- if (sig[i].wire == nullptr) {
- if (wire->port_output)
- sig[i] = SigBit(wire, i);
- else
- continue;
- }
-
- if (input_bits.count(sig[i]) || ci_bits.count(SigSpec(sig[i]))) {
+ RTLIL::SigBit b(wire, i);
+ if (input_bits.count(b) || ci_bits.count(b)) {
int a = aig_map.at(sig[i]);
log_assert((a & 1) == 0);
if (GetSize(wire) != 1)
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
}
- if (output_bits.count(SigSpec(wire, i)) || co_bits.count(SigSpec(wire, i))) {
- int o = ordered_outputs.at(SigSpec(wire, i));
+ if (output_bits.count(b) || co_bits.count(b)) {
+ int o = ordered_outputs.at(b);
+ output_seen = !miter_mode;
if (GetSize(wire) != 1)
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
else
}
}
+ if (omode && !output_seen)
+ symbols["o0"].push_back("__dummy_o__");
+
symbols.sort();
for (auto &sym : symbols) {
log_error("Can't find top module in current design!\n");
XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
- writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
+ writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
if (!map_filename.empty()) {
std::ofstream mapf;
projects / yosys.git / blobdiff