* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
pool<SigBit> input_bits, output_bits;
dict<SigBit, SigBit> not_map, ff_map, alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
- vector<pair<SigBit, SigBit>> asserts, assumes;
- vector<pair<SigBit, SigBit>> liveness, fairness;
pool<SigBit> initstate_bits;
+ pool<SigBit> ci_bits, co_bits;
+ dict<IdString, unsigned> type_map;
vector<pair<int, int>> aig_gates;
vector<int> aig_latchin, aig_latchinit, aig_outputs;
int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
- int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
dict<SigBit, int> aig_map;
dict<SigBit, int> ordered_outputs;
}
}
- for (auto bit : input_bits)
- undriven_bits.erase(bit);
+ for (auto bit : input_bits) {
+ if (!bit.wire->port_output)
+ undriven_bits.erase(bit);
+ // Erase POs that are also PIs
+ output_bits.erase(bit);
+ }
for (auto bit : output_bits)
- unused_bits.erase(bit);
+ if (!bit.wire->port_input)
+ unused_bits.erase(bit);
for (auto cell : module->cells())
{
continue;
}
- if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
- {
- SigBit D = sigmap(cell->getPort("\\D").as_bit());
- SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
- unused_bits.erase(D);
- undriven_bits.erase(Q);
- ff_map[Q] = D;
- continue;
- }
+ //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
+ //{
+ // SigBit D = sigmap(cell->getPort("\\D").as_bit());
+ // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
+ // unused_bits.erase(D);
+ // undriven_bits.erase(Q);
+ // ff_map[Q] = D;
+ // continue;
+ //}
if (cell->type == "$_AND_")
{
continue;
}
- log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
+ for (const auto &c : cell->connections()) {
+ if (c.second.is_fully_const()) continue;
+ for (auto b : c.second.bits()) {
+ Wire *w = b.wire;
+ if (!w) continue;
+ auto is_input = cell->input(c.first);
+ auto is_output = cell->output(c.first);
+ log_assert(is_input || is_output);
+ if (is_input) {
+ if (!w->port_input) {
+ SigBit I = sigmap(b);
+ if (I != b)
+ alias_map[b] = I;
+ if (!output_bits.count(b))
+ co_bits.insert(b);
+ }
+ }
+ if (is_output) {
+ SigBit O = sigmap(b);
+ if (!input_bits.count(O))
+ ci_bits.insert(O);
+ }
+ }
+ if (!type_map.count(cell->type))
+ type_map[cell->type] = type_map.size()+1;
+ }
+ //log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
+ }
+
+ for (auto bit : input_bits) {
+ RTLIL::Wire *wire = bit.wire;
+ // If encountering an inout port, then create a new wire with $inout.out
+ // suffix, make it a CO driven by the existing inout, and inherit existing
+ // inout's drivers
+ if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
+ RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
+ if (!new_wire)
+ new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
+ SigBit new_bit(new_wire, bit.offset);
+ module->connect(new_bit, bit);
+ if (not_map.count(bit))
+ not_map[new_bit] = not_map.at(bit);
+ else if (and_map.count(bit))
+ and_map[new_bit] = and_map.at(bit);
+ else if (alias_map.count(bit))
+ alias_map[new_bit] = alias_map.at(bit);
+ co_bits.insert(new_bit);
+ }
+ }
+
+ // Do some CI/CO post-processing:
+ // Erase all POs and COs that are undriven
+ for (auto bit : undriven_bits) {
+ co_bits.erase(bit);
+ output_bits.erase(bit);
}
+ // Erase all CIs that are also COs
+ for (auto bit : co_bits)
+ ci_bits.erase(bit);
+ // CIs cannot be undriven
+ for (auto bit : ci_bits)
+ undriven_bits.erase(bit);
for (auto bit : unused_bits)
undriven_bits.erase(bit);
aig_map[bit] = 2*aig_m;
}
+ for (auto bit : ci_bits) {
+ aig_m++, aig_i++;
+ aig_map[bit] = 2*aig_m;
+ }
+
if (imode && input_bits.empty()) {
aig_m++, aig_i++;
}
}
}
- int fair_live_inputs_cnt = GetSize(liveness);
- int fair_live_inputs_m = aig_m;
-
- aig_m += fair_live_inputs_cnt;
- aig_i += fair_live_inputs_cnt;
-
for (auto it : ff_map) {
aig_m++, aig_l++;
aig_map[it.first] = 2*aig_m;
aig_latchinit.push_back(0);
}
- int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness);
- int fair_live_latches_m = aig_m;
- int fair_live_latches_l = aig_l;
-
- aig_m += fair_live_latches_cnt;
- aig_l += fair_live_latches_cnt;
-
- for (int i = 0; i < fair_live_latches_cnt; i++)
- aig_latchinit.push_back(0);
-
if (zinit_mode)
{
for (auto it : ff_map)
if (!initstate_bits.empty() || !init_inputs.empty())
aig_latchin.push_back(1);
- for (auto bit : output_bits) {
+ for (auto bit : co_bits) {
aig_o++;
ordered_outputs[bit] = aig_o-1;
aig_outputs.push_back(bit2aig(bit));
}
- if (omode && output_bits.empty()) {
+ for (auto bit : output_bits) {
aig_o++;
- aig_outputs.push_back(0);
- }
-
- for (auto it : asserts) {
- aig_b++;
- int bit_a = bit2aig(it.first);
- int bit_en = bit2aig(it.second);
- aig_outputs.push_back(mkgate(bit_a^1, bit_en));
+ ordered_outputs[bit] = aig_o-1;
+ aig_outputs.push_back(bit2aig(bit));
}
- if (bmode && asserts.empty()) {
- aig_b++;
+ if (omode && output_bits.empty() && co_bits.empty()) {
+ aig_o++;
aig_outputs.push_back(0);
}
- for (auto it : assumes) {
- aig_c++;
- int bit_a = bit2aig(it.first);
- int bit_en = bit2aig(it.second);
- aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1);
- }
-
- for (auto it : liveness)
- {
- int input_m = ++fair_live_inputs_m;
- int latch_m1 = ++fair_live_latches_m;
- int latch_m2 = ++fair_live_latches_m;
-
- log_assert(GetSize(aig_latchin) == fair_live_latches_l);
- fair_live_latches_l += 2;
-
- int bit_a = bit2aig(it.first);
- int bit_en = bit2aig(it.second);
- int bit_s = 2*input_m;
- int bit_q1 = 2*latch_m1;
- int bit_q2 = 2*latch_m2;
-
- int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1;
- int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1;
-
- aig_j++;
- aig_latchin.push_back(bit_d1);
- aig_latchin.push_back(bit_d2);
- aig_outputs.push_back(mkgate(bit_q1, bit_q2^1));
- }
-
- for (auto it : fairness)
- {
- int latch_m = ++fair_live_latches_m;
-
- log_assert(GetSize(aig_latchin) == fair_live_latches_l);
- fair_live_latches_l += 1;
-
- int bit_a = bit2aig(it.first);
- int bit_en = bit2aig(it.second);
- int bit_q = 2*latch_m;
-
- aig_f++;
- aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1));
- aig_outputs.push_back(bit_q^1);
+ if (bmode) {
+ //aig_b++;
+ aig_outputs.push_back(0);
}
}
- void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
+ void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
{
- int aig_obc = aig_o + aig_b + aig_c;
- int aig_obcj = aig_obc + aig_j;
- int aig_obcjf = aig_obcj + aig_f;
+ int aig_obc = aig_o;
+ int aig_obcj = aig_obc;
+ int aig_obcjf = aig_obcj;
log_assert(aig_m == aig_i + aig_l + aig_a);
log_assert(aig_l == GetSize(aig_latchin));
log_assert(aig_l == GetSize(aig_latchinit));
log_assert(aig_obcjf == GetSize(aig_outputs));
- if (miter_mode) {
- if (aig_b || aig_c || aig_j || aig_f)
- log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
- f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
- } else {
- f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
- if (aig_b || aig_c || aig_j || aig_f)
- f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
- f << stringf("\n");
- }
+ f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
+ f << stringf("\n");
if (ascii_mode)
{
{
dict<string, vector<string>> symbols;
+ bool output_seen = false;
for (auto wire : module->wires())
{
- if (wire->name[0] == '$')
- continue;
+ //if (wire->name[0] == '$')
+ // continue;
SigSpec sig = sigmap(wire);
for (int i = 0; i < GetSize(wire); i++)
{
- if (sig[i].wire == nullptr) {
- if (wire->port_output)
- sig[i] = SigBit(wire, i);
- else
- continue;
- }
-
- if (wire->port_input) {
+ RTLIL::SigBit b(wire, i);
+ if (input_bits.count(b) || ci_bits.count(b)) {
int a = aig_map.at(sig[i]);
log_assert((a & 1) == 0);
if (GetSize(wire) != 1)
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
}
- if (wire->port_output) {
- int o = ordered_outputs.at(SigSpec(wire, i));
+ if (output_bits.count(b) || co_bits.count(b)) {
+ int o = ordered_outputs.at(b);
+ output_seen = !miter_mode;
if (GetSize(wire) != 1)
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
else
}
}
+ if (omode && !output_seen)
+ symbols["o0"].push_back("__dummy_o__");
+
symbols.sort();
for (auto &sym : symbols) {
f << stringf("c\nGenerated by %s\n", yosys_version_str);
}
- void write_map(std::ostream &f, bool verbose_map)
+ void write_map(std::ostream &f, bool verbose_map, bool omode)
{
dict<int, string> input_lines;
dict<int, string> init_lines;
for (auto wire : module->wires())
{
- if (!verbose_map && wire->name[0] == '$')
- continue;
+ //if (!verbose_map && wire->name[0] == '$')
+ // continue;
SigSpec sig = sigmap(wire);
for (int i = 0; i < GetSize(wire); i++)
{
- if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
- continue;
-
- int a = aig_map.at(sig[i]);
-
- if (verbose_map)
- wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
-
- if (wire->port_input) {
+ RTLIL::SigBit b(wire, i);
+ if (input_bits.count(b) || ci_bits.count(b)) {
+ int a = aig_map.at(sig[i]);
log_assert((a & 1) == 0);
input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+ continue;
}
- if (wire->port_output) {
- int o = ordered_outputs.at(sig[i]);
+ if (output_bits.count(b) || co_bits.count(b)) {
+ int o = ordered_outputs.at(b);
output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
+ continue;
}
if (init_inputs.count(sig[i])) {
int a = init_inputs.at(sig[i]);
log_assert((a & 1) == 0);
init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+ continue;
}
if (ordered_latches.count(sig[i])) {
latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
else
latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
+ continue;
+ }
+
+ if (verbose_map) {
+ if (aig_map.count(sig[i]) == 0)
+ continue;
+
+ int a = aig_map.at(sig[i]);
+ wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
}
}
}
input_lines.sort();
for (auto &it : input_lines)
f << it.second;
+ log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
init_lines.sort();
for (auto &it : init_lines)
output_lines.sort();
for (auto &it : output_lines)
f << it.second;
+ log_assert(output_lines.size() == output_bits.size() + co_bits.size());
+ if (omode && output_lines.empty())
+ f << "output 0 0 __dummy_o__\n";
latch_lines.sort();
for (auto &it : latch_lines)
log_error("Can't find top module in current design!\n");
XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
- writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
+ writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
if (!map_filename.empty()) {
std::ofstream mapf;
mapf.open(map_filename.c_str(), std::ofstream::trunc);
if (mapf.fail())
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
- writer.write_map(mapf, verbose_map);
+ writer.write_map(mapf, verbose_map, omode);
}
}
} XAigerBackend;
projects / yosys.git / blobdiff