/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
struct XAigerWriter
{
+ Design *design;
Module *module;
SigMap sigmap;
dict<SigBit, SigBit> not_map, alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
vector<SigBit> ci_bits, co_bits;
- dict<SigBit, Cell*> ff_bits;
+ vector<Cell*> ff_list;
dict<SigBit, float> arrival_times;
vector<pair<int, int>> aig_gates;
return a;
}
- XAigerWriter(Module *module, bool dff_mode, bool holes_mode=false) : module(module), sigmap(module)
+ XAigerWriter(Module *module, bool dff_mode) : design(module->design), module(module), sigmap(module)
{
pool<SigBit> undriven_bits;
pool<SigBit> unused_bits;
// promote public wires
for (auto wire : module->wires())
- if (wire->name[0] == '\\')
+ if (wire->name.isPublic())
sigmap.add(wire);
// promote input wires
undriven_bits.insert(bit);
unused_bits.insert(bit);
- bool scc = wire->attributes.count(ID::abc9_scc);
- if (wire->port_input || scc)
+ if (wire->port_input)
input_bits.insert(bit);
bool keep = wire->get_bool_attribute(ID::keep);
- if (wire->port_output || keep || scc) {
+ if (wire->port_output || keep) {
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
continue;
}
- if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+ if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
{
SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
- auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
- log_assert(r.second);
+ ff_list.emplace_back(cell);
continue;
}
continue;
}
- RTLIL::Module* inst_module = module->design->module(cell->type);
- if (inst_module) {
- IdString derived_type;
- if (cell->parameters.empty())
- derived_type = cell->type;
- else
- derived_type = inst_module->derive(module->design, cell->parameters);
- inst_module = module->design->module(derived_type);
- log_assert(inst_module);
-
+ RTLIL::Module* inst_module = design->module(cell->type);
+ if (inst_module && inst_module->get_blackbox_attribute()) {
bool abc9_flop = false;
- if (!cell->has_keep_attr()) {
- auto it = cell->attributes.find(ID::abc9_box_seq);
- if (it != cell->attributes.end()) {
- int abc9_box_seq = it->second.as_int();
- if (GetSize(box_list) <= abc9_box_seq)
- box_list.resize(abc9_box_seq+1);
- box_list[abc9_box_seq] = cell;
- // Only flop boxes may have arrival times
- // (all others are combinatorial)
- abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
- if (!abc9_flop)
- continue;
- }
+
+ auto it = cell->attributes.find(ID::abc9_box_seq);
+ if (it != cell->attributes.end()) {
+ log_assert(!cell->has_keep_attr());
+ log_assert(cell->parameters.empty());
+ int abc9_box_seq = it->second.as_int();
+ if (GetSize(box_list) <= abc9_box_seq)
+ box_list.resize(abc9_box_seq+1);
+ box_list[abc9_box_seq] = cell;
+ // Only flop boxes may have arrival times
+ // (all others are combinatorial)
+ log_assert(cell->parameters.empty());
+ abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
+ if (!abc9_flop)
+ continue;
}
- if (!timing.count(derived_type))
+ if (!timing.count(inst_module->name))
timing.setup_module(inst_module);
- auto &t = timing.at(derived_type).arrival;
- for (const auto &conn : cell->connections()) {
- auto port_wire = inst_module->wire(conn.first);
- if (!port_wire->port_output)
+
+ for (auto &i : timing.at(inst_module->name).arrival) {
+ if (!cell->hasPort(i.first.name))
continue;
- for (int i = 0; i < GetSize(conn.second); i++) {
- auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
- if (d == 0)
- continue;
+ auto port_wire = inst_module->wire(i.first.name);
+ log_assert(port_wire->port_output);
+
+ auto d = i.second.first;
+ if (d == 0)
+ continue;
+ auto offset = i.first.offset;
#ifndef NDEBUG
- if (ys_debug(1)) {
- static std::set<std::tuple<IdString,IdString,int>> seen;
- if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
- log_id(cell->type), log_id(conn.first), i, d);
- }
-#endif
- arrival_times[conn.second[i]] = d;
+ if (ys_debug(1)) {
+ static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
+ if (seen.emplace(inst_module->name, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
+ log_id(cell->type), log_id(i.first.name), offset, d);
}
+#endif
+ arrival_times[cell->getPort(i.first.name)[offset]] = d;
}
if (abc9_flop)
continue;
}
- else {
- if (cell->type == ID($__ABC9_DELAY))
- log_error("Cell type '%s' not recognised. Check that '+/abc9_model.v' has been read.\n", cell->type.c_str());
- }
bool cell_known = inst_module || cell->known();
for (const auto &c : cell->connections()) {
for (auto cell : box_list) {
log_assert(cell);
- RTLIL::Module* box_module = module->design->module(cell->type);
+ RTLIL::Module* box_module = design->module(cell->type);
log_assert(box_module);
- log_assert(box_module->attributes.count(ID::abc9_box_id));
+ log_assert(box_module->has_attribute(ID::abc9_box_id));
auto r = box_ports.insert(cell->type);
if (r.second) {
undriven_bits.erase(bit);
}
- if (holes_mode) {
- struct sort_by_port_id {
- bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
- return a.wire->port_id < b.wire->port_id ||
- (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
- }
- };
- input_bits.sort(sort_by_port_id());
- output_bits.sort(sort_by_port_id());
- }
+ struct sort_by_port_id {
+ bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
+ return a.wire->port_id < b.wire->port_id ||
+ (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
+ }
+ };
+ input_bits.sort(sort_by_port_id());
+ output_bits.sort(sort_by_port_id());
aig_map[State::S0] = 0;
aig_map[State::S1] = 1;
aig_map[bit] = 2*aig_m;
}
- for (const auto &i : ff_bits) {
- const Cell *cell = i.second;
+ for (auto cell : ff_list) {
const SigBit &q = sigmap(cell->getPort(ID::Q));
aig_m++, aig_i++;
log_assert(!aig_map.count(q));
// that has been padded to its full width
if (bit == State::Sx)
continue;
- log_assert(!aig_map.count(bit));
+ if (aig_map.count(bit))
+ log_error("Visited AIG node more than once; this could be a combinatorial loop that has not been broken\n");
aig_map[bit] = 2*aig_m;
}
aig_outputs.push_back(aig);
}
- for (auto &i : ff_bits) {
- const SigBit &d = i.first;
+ for (auto cell : ff_list) {
+ const SigBit &d = sigmap(cell->getPort(ID::D));
aig_o++;
aig_outputs.push_back(aig_map.at(d));
}
std::stringstream h_buffer;
auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
write_h_buffer(1);
- log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
- write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
- log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
- write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
- log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
- write_h_buffer(input_bits.size() + ff_bits.size());
- log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
- write_h_buffer(output_bits.size() + ff_bits.size());
+ log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
+ write_h_buffer(GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
+ log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
+ write_h_buffer(GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
+ log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_list));
+ write_h_buffer(GetSize(input_bits) + GetSize(ff_list));
+ log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_list));
+ write_h_buffer(GetSize(output_bits) + GetSize(ff_list));
log_debug("boxNum = %d\n", GetSize(box_list));
- write_h_buffer(box_list.size());
+ write_h_buffer(GetSize(box_list));
auto write_buffer_float = [](std::stringstream &buffer, float f32) {
buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
//for (auto bit : output_bits)
// write_o_buffer(0);
- if (!box_list.empty() || !ff_bits.empty()) {
+ if (!box_list.empty() || !ff_list.empty()) {
dict<IdString, std::tuple<int,int,int>> cell_cache;
int box_count = 0;
for (auto cell : box_list) {
log_assert(cell);
+ log_assert(cell->parameters.empty());
- RTLIL::Module* box_module = module->design->module(cell->type);
- log_assert(box_module);
-
- IdString derived_type;
- if (cell->parameters.empty())
- derived_type = cell->type;
- else
- derived_type = box_module->derive(module->design, cell->parameters);
- box_module = box_module->design->module(derived_type);
- log_assert(box_module);
-
- auto r = cell_cache.insert(derived_type);
+ auto r = cell_cache.insert(cell->type);
auto &v = r.first->second;
if (r.second) {
+ RTLIL::Module* box_module = design->module(cell->type);
+ log_assert(box_module);
+
int box_inputs = 0, box_outputs = 0;
for (auto port_name : box_module->ports) {
RTLIL::Wire *w = box_module->wire(port_name);
std::stringstream r_buffer;
auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
- log_debug("flopNum = %d\n", GetSize(ff_bits));
- write_r_buffer(ff_bits.size());
+ log_debug("flopNum = %d\n", GetSize(ff_list));
+ write_r_buffer(ff_list.size());
std::stringstream s_buffer;
auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
- write_s_buffer(ff_bits.size());
-
- dict<SigBit, int> clk_to_mergeability;
- for (const auto &i : ff_bits) {
- const Cell *cell = i.second;
- log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_)));
-
- SigBit clock = sigmap(cell->getPort(ID::C));
- clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size()*2+1));
- }
+ write_s_buffer(ff_list.size());
- for (const auto &i : ff_bits) {
- const SigBit &d = i.first;
- const Cell *cell = i.second;
+ dict<SigSpec, int> clk_to_mergeability;
+ for (const auto cell : ff_list) {
+ const SigBit &d = sigmap(cell->getPort(ID::D));
+ const SigBit &q = sigmap(cell->getPort(ID::Q));
- SigBit clock = sigmap(cell->getPort(ID::C));
- int mergeability = clk_to_mergeability.at(clock);
+ SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
+ auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
+ int mergeability = r.first->second;
log_assert(mergeability > 0);
- if (cell->type == ID($_DFF_N_))
- write_r_buffer(mergeability);
- else if (cell->type == ID($_DFF_P_))
- write_r_buffer(mergeability+1);
- else log_abort();
-
- SigBit Q = sigmap(cell->getPort(ID::Q));
- State init = init_map.at(Q, State::Sx);
+ write_r_buffer(mergeability);
+
+ State init = init_map.at(q, State::Sx);
+ log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
if (init == State::S1)
write_s_buffer(1);
else if (init == State::S0)
RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
if (holes_module) {
std::stringstream a_buffer;
- XAigerWriter writer(holes_module, false /* dff_mode */, true /* holes_mode */);
+ XAigerWriter writer(holes_module, false /* dff_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);
f << "a";
f << stringf("Generated by %s\n", yosys_version_str);
- module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
- module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
- module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
- module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
+ design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
+ design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
+ design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
+ design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
}
void write_map(std::ostream &f)
for (auto wire : module->wires())
{
- SigSpec sig = sigmap(wire);
-
for (int i = 0; i < GetSize(wire); i++)
{
RTLIL::SigBit b(wire, i);
if (output_bits.count(b)) {
int o = ordered_outputs.at(b);
output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
- continue;
}
}
}
struct XAigerBackend : public Backend {
XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" write $_DFF_[NP]_ cells\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool ascii_mode = false, dff_mode = false;
std::string map_filename;
projects / yosys.git / blobdiff