SigMap sigmap;
RTLIL::Module *module;
bool verbose;
+ bool single_bad;
int next_nid = 1;
int initstate_nid = -1;
vector<pair<int, Cell*>> ff_todo;
pool<Cell*> cell_recursion_guard;
- pool<string> output_symbols;
+ vector<int> bad_properties;
+ dict<SigBit, bool> initbits;
+ pool<Wire*> statewires;
string indent;
void btorf(const char *fmt, ...)
return sorts_bv.at(width);
}
+ int get_mem_sid(int abits, int dbits)
+ {
+ pair<int, int> key(abits, dbits);
+ if (sorts_mem.count(key) == 0) {
+ int addr_sid = get_bv_sid(abits);
+ int data_sid = get_bv_sid(dbits);
+ int nid = next_nid++;
+ btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
+ sorts_mem[key] = nid;
+ }
+ return sorts_mem.at(key);
+ }
+
void add_nid_sig(int nid, const SigSpec &sig)
{
+ if (verbose)
+ f << indent << stringf("; %d %s\n", nid, log_signal(sig));
+
for (int i = 0; i < GetSize(sig); i++)
bit_nid[sig[i]] = make_pair(nid, i);
void export_cell(Cell *cell)
{
- log_assert(cell_recursion_guard.count(cell) == 0);
+ if (cell_recursion_guard.count(cell)) {
+ string cell_list;
+ for (auto c : cell_recursion_guard)
+ cell_list += stringf("\n %s", log_id(c));
+ log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
+ }
+
cell_recursion_guard.insert(cell);
btorf_push(log_id(cell));
- if (cell->type.in("$add", "$sub", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
- "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
+ if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
+ "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
{
string btor_op;
if (cell->type == "$add") btor_op = "add";
if (cell->type == "$sub") btor_op = "sub";
+ if (cell->type == "$mul") btor_op = "mul";
if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
if (cell->type == "$shr") btor_op = "srl";
if (cell->type == "$sshr") btor_op = "sra";
if (cell->type.in("$and", "$_AND_")) btor_op = "and";
if (cell->type.in("$or", "$_OR_")) btor_op = "or";
if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
+ if (cell->type == "$concat") btor_op = "concat";
if (cell->type == "$_NAND_") btor_op = "nand";
if (cell->type == "$_NOR_") btor_op = "nor";
if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
goto okay;
}
+ if (cell->type.in("$div", "$mod"))
+ {
+ string btor_op;
+ if (cell->type == "$div") btor_op = "div";
+ if (cell->type == "$mod") btor_op = "rem";
+ log_assert(!btor_op.empty());
+
+ int width = GetSize(cell->getPort("\\Y"));
+ width = std::max(width, GetSize(cell->getPort("\\A")));
+ width = std::max(width, GetSize(cell->getPort("\\B")));
+
+ bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
+ bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
+
+ int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
+ int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
+
+ int sid = get_bv_sid(width);
+ int nid = next_nid++;
+ btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
+
+ SigSpec sig = sigmap(cell->getPort("\\Y"));
+
+ if (GetSize(sig) < width) {
+ int sid = get_bv_sid(GetSize(sig));
+ int nid2 = next_nid++;
+ btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
+ nid = nid2;
+ }
+
+ add_nid_sig(nid, sig);
+ goto okay;
+ }
+
if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
{
int sid = get_bv_sid(1);
if (cell->type == "$lt") btor_op = "lt";
if (cell->type == "$le") btor_op = "lte";
if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
- if (cell->type.in("$ne", "$nex")) btor_op = "ne";
+ if (cell->type.in("$ne", "$nex")) btor_op = "neq";
if (cell->type == "$ge") btor_op = "gte";
if (cell->type == "$gt") btor_op = "gt";
log_assert(!btor_op.empty());
SigSpec sig_d = sigmap(cell->getPort("\\D"));
SigSpec sig_q = sigmap(cell->getPort("\\Q"));
- string symbol = log_signal(sig_q);
- if (symbol.find(' ') != string::npos)
- symbol = log_id(cell);
+ IdString symbol;
+
+ if (sig_q.is_wire()) {
+ Wire *w = sig_q.as_wire();
+ if (w->port_id == 0) {
+ statewires.insert(w);
+ symbol = w->name;
+ }
+ }
+
+ Const initval;
+ for (int i = 0; i < GetSize(sig_q); i++)
+ if (initbits.count(sig_q[i]))
+ initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
+ else
+ initval.bits.push_back(State::Sx);
+
+ int nid_init_val = -1;
- if (symbol[0] == '\\')
- symbol = symbol.substr(1);
+ if (!initval.is_fully_undef())
+ nid_init_val = get_sig_nid(initval);
int sid = get_bv_sid(GetSize(sig_q));
int nid = next_nid++;
- if (output_symbols.count(symbol))
+ if (symbol.empty())
btorf("%d state %d\n", nid, sid);
else
- btorf("%d state %d %s\n", nid, sid, symbol.c_str());
+ btorf("%d state %d %s\n", nid, sid, log_id(symbol));
+
+ if (nid_init_val >= 0) {
+ int nid_init = next_nid++;
+ if (verbose)
+ btorf("; initval = %s\n", log_signal(initval));
+ btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
+ }
ff_todo.push_back(make_pair(nid, cell));
add_nid_sig(nid, sig_q);
goto okay;
}
+ if (cell->type.in("$anyconst", "$anyseq"))
+ {
+ SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+
+ int sid = get_bv_sid(GetSize(sig_y));
+ int nid = next_nid++;
+
+ btorf("%d state %d\n", nid, sid);
+
+ if (cell->type == "$anyconst") {
+ int nid2 = next_nid++;
+ btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
+ }
+
+ add_nid_sig(nid, sig_y);
+ goto okay;
+ }
+
if (cell->type == "$initstate")
{
SigSpec sig_y = sigmap(cell->getPort("\\Y"));
goto okay;
}
+ if (cell->type == "$mem")
+ {
+ int abits = cell->getParam("\\ABITS").as_int();
+ int width = cell->getParam("\\WIDTH").as_int();
+ int nwords = cell->getParam("\\SIZE").as_int();
+ int rdports = cell->getParam("\\RD_PORTS").as_int();
+ int wrports = cell->getParam("\\WR_PORTS").as_int();
+
+ Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
+ Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
+
+ bool asyncwr = wr_clk_en.is_fully_zero();
+
+ if (!asyncwr && !wr_clk_en.is_fully_ones())
+ log_error("Memory %s.%s has mixed async/sync write ports.\n",
+ log_id(module), log_id(cell));
+
+ if (!rd_clk_en.is_fully_zero())
+ log_error("Memory %s.%s has sync read ports.\n",
+ log_id(module), log_id(cell));
+
+ SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
+ SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
+
+ SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
+ SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
+ SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
+
+ int data_sid = get_bv_sid(width);
+ int bool_sid = get_bv_sid(1);
+ int sid = get_mem_sid(abits, width);
+
+ Const initdata = cell->getParam("\\INIT");
+ initdata.exts(nwords*width);
+ int nid_init_val = -1;
+
+ if (!initdata.is_fully_undef())
+ {
+ bool constword = true;
+ Const firstword = initdata.extract(0, width);
+
+ for (int i = 1; i < nwords; i++) {
+ Const thisword = initdata.extract(i*width, width);
+ if (thisword != firstword) {
+ constword = false;
+ break;
+ }
+ }
+
+ if (constword)
+ {
+ if (verbose)
+ btorf("; initval = %s\n", log_signal(firstword));
+ nid_init_val = get_sig_nid(firstword);
+ }
+ else
+ {
+ int nid_init_val = next_nid++;
+ btorf("%d state %d\n", nid_init_val, sid);
+
+ for (int i = 0; i < nwords; i++) {
+ Const thisword = initdata.extract(i*width, width);
+ if (thisword.is_fully_undef())
+ continue;
+ Const thisaddr(i, abits);
+ int nid_thisword = get_sig_nid(thisword);
+ int nid_thisaddr = get_sig_nid(thisaddr);
+ int last_nid_init_val = nid_init_val;
+ nid_init_val = next_nid++;
+ if (verbose)
+ btorf("; initval[%d] = %s\n", i, log_signal(thisword));
+ btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
+ }
+ }
+ }
+
+
+ int nid = next_nid++;
+ int nid_head = nid;
+
+ if (cell->name[0] == '$')
+ btorf("%d state %d\n", nid, sid);
+ else
+ btorf("%d state %d %s\n", nid, sid, log_id(cell));
+
+ if (nid_init_val >= 0)
+ {
+ int nid_init = next_nid++;
+ btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
+ }
+
+ if (asyncwr)
+ {
+ for (int port = 0; port < wrports; port++)
+ {
+ SigSpec wa = sig_wr_addr.extract(port*abits, abits);
+ SigSpec wd = sig_wr_data.extract(port*width, width);
+ SigSpec we = sig_wr_en.extract(port*width, width);
+
+ int wa_nid = get_sig_nid(wa);
+ int wd_nid = get_sig_nid(wd);
+ int we_nid = get_sig_nid(we);
+
+ int nid2 = next_nid++;
+ btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
+
+ int nid3 = next_nid++;
+ btorf("%d not %d %d\n", nid3, data_sid, we_nid);
+
+ int nid4 = next_nid++;
+ btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
+
+ int nid5 = next_nid++;
+ btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
+
+ int nid6 = next_nid++;
+ btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
+
+ int nid7 = next_nid++;
+ btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
+
+ int nid8 = next_nid++;
+ btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
+
+ int nid9 = next_nid++;
+ btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
+
+ nid_head = nid9;
+ }
+ }
+
+ for (int port = 0; port < rdports; port++)
+ {
+ SigSpec ra = sig_rd_addr.extract(port*abits, abits);
+ SigSpec rd = sig_rd_data.extract(port*width, width);
+
+ int ra_nid = get_sig_nid(ra);
+ int rd_nid = next_nid++;
+
+ btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
+
+ add_nid_sig(rd_nid, rd);
+ }
+
+ if (!asyncwr)
+ {
+ ff_todo.push_back(make_pair(nid, cell));
+ }
+ else
+ {
+ int nid2 = next_nid++;
+ btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
+ }
+
+ goto okay;
+ }
+
log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
okay:
int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false)
{
+ int nid = -1;
sigmap.apply(sig);
+ for (auto bit : sig)
+ if (bit == State::Sx)
+ goto has_undef_bits;
+
+ if (0)
+ {
+ has_undef_bits:
+ SigSpec sig_mask_undef, sig_noundef;
+ int first_undef = -1;
+
+ for (int i = 0; i < GetSize(sig); i++)
+ if (sig[i] == State::Sx) {
+ if (first_undef < 0)
+ first_undef = i;
+ sig_mask_undef.append(State::S1);
+ sig_noundef.append(State::S0);
+ } else {
+ sig_mask_undef.append(State::S0);
+ sig_noundef.append(sig[i]);
+ }
+
+ if (to_width < 0 || first_undef < to_width)
+ {
+ int sid = get_bv_sid(GetSize(sig));
+
+ int nid_input = next_nid++;
+ btorf("%d input %d\n", nid_input, sid);
+
+ int nid_masked_input;
+ if (sig_mask_undef.is_fully_ones()) {
+ nid_masked_input = nid_input;
+ } else {
+ int nid_mask_undef = get_sig_nid(sig_mask_undef);
+ nid_masked_input = next_nid++;
+ btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
+ }
+
+ if (sig_noundef.is_fully_zero()) {
+ nid = nid_masked_input;
+ } else {
+ int nid_noundef = get_sig_nid(sig_noundef);
+ nid = next_nid++;
+ btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
+ }
+
+ goto extend_or_trim;
+ }
+
+ sig = sig_noundef;
+ }
+
if (sig_nid.count(sig) == 0)
{
// <nid>, <bitidx>
}
else
{
+ if (bit_cell.count(bit) == 0)
+ log_error("No driver for signal bit %s.\n", log_signal(bit));
export_cell(bit_cell.at(bit));
log_assert(bit_nid.count(bit));
}
nid_width[nid] = width;
}
- int nid = sig_nid.at(sig);
+ nid = sig_nid.at(sig);
+ extend_or_trim:
if (to_width >= 0 && to_width != GetSize(sig))
{
if (to_width < GetSize(sig))
return nid;
}
- BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose) :
- f(f), sigmap(module), module(module), verbose(verbose)
+ BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) :
+ f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad)
{
btorf_push("inputs");
for (auto wire : module->wires())
{
+ if (wire->attributes.count("\\init")) {
+ Const attrval = wire->attributes.at("\\init");
+ for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
+ if (attrval[i] == State::S0 || attrval[i] == State::S1)
+ initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
+ }
+
if (!wire->port_id || !wire->port_input)
continue;
bit_cell[bit] = cell;
}
- for (auto wire : module->wires())
- if (wire->port_output)
- output_symbols.insert(log_id(wire));
-
for (auto wire : module->wires())
{
if (!wire->port_id || !wire->port_output)
btorf_push(stringf("output %s", log_id(wire)));
- int sid = get_bv_sid(GetSize(wire));
int nid = get_sig_nid(wire);
- btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire));
+ btorf("%d output %d %s\n", next_nid++, nid, log_id(wire));
btorf_pop(stringf("output %s", log_id(wire)));
}
int nid_en = get_sig_nid(cell->getPort("\\EN"));
int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++;
- int nid = next_nid++;
btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
- btorf("%d bad %d\n", nid, nid_en_and_not_a);
+
+ if (single_bad) {
+ bad_properties.push_back(nid_en_and_not_a);
+ } else {
+ int nid = next_nid++;
+ btorf("%d bad %d\n", nid, nid_en_and_not_a);
+ }
btorf_pop(log_id(cell));
}
}
+ for (auto wire : module->wires())
+ {
+ if (wire->port_id || wire->name[0] == '$')
+ continue;
+
+ btorf_push(stringf("wire %s", log_id(wire)));
+
+ int sid = get_bv_sid(GetSize(wire));
+ int nid = get_sig_nid(sigmap(wire));
+
+ if (statewires.count(wire))
+ continue;
+
+ int this_nid = next_nid++;
+ btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire));
+
+ btorf_pop(stringf("wire %s", log_id(wire)));
+ continue;
+ }
+
while (!ff_todo.empty())
{
vector<pair<int, Cell*>> todo;
for (auto &it : todo)
{
- btorf_push(stringf("next %s", log_id(it.second)));
+ int nid = it.first;
+ Cell *cell = it.second;
- SigSpec sig = sigmap(it.second->getPort("\\D"));
+ btorf_push(stringf("next %s", log_id(cell)));
- int nid = get_sig_nid(sig);
- int sid = get_bv_sid(GetSize(sig));
- btorf("%d next %d %d %d\n", next_nid++, sid, it.first, nid);
+ if (cell->type == "$mem")
+ {
+ int abits = cell->getParam("\\ABITS").as_int();
+ int width = cell->getParam("\\WIDTH").as_int();
+ int wrports = cell->getParam("\\WR_PORTS").as_int();
+
+ SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
+ SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
+ SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
+
+ int data_sid = get_bv_sid(width);
+ int bool_sid = get_bv_sid(1);
+ int sid = get_mem_sid(abits, width);
+ int nid_head = nid;
+
+ for (int port = 0; port < wrports; port++)
+ {
+ SigSpec wa = sig_wr_addr.extract(port*abits, abits);
+ SigSpec wd = sig_wr_data.extract(port*width, width);
+ SigSpec we = sig_wr_en.extract(port*width, width);
+
+ int wa_nid = get_sig_nid(wa);
+ int wd_nid = get_sig_nid(wd);
+ int we_nid = get_sig_nid(we);
+
+ int nid2 = next_nid++;
+ btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
+
+ int nid3 = next_nid++;
+ btorf("%d not %d %d\n", nid3, data_sid, we_nid);
+
+ int nid4 = next_nid++;
+ btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
+
+ int nid5 = next_nid++;
+ btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
+
+ int nid6 = next_nid++;
+ btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
+
+ int nid7 = next_nid++;
+ btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
+
+ int nid8 = next_nid++;
+ btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
- btorf_pop(stringf("next %s", log_id(it.second)));
+ int nid9 = next_nid++;
+ btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
+
+ nid_head = nid9;
+ }
+
+ int nid2 = next_nid++;
+ btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
+ }
+ else
+ {
+ SigSpec sig = sigmap(cell->getPort("\\D"));
+ int nid_q = get_sig_nid(sig);
+ int sid = get_bv_sid(GetSize(sig));
+ btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q);
+ }
+
+ btorf_pop(stringf("next %s", log_id(cell)));
+ }
+ }
+
+ while (!bad_properties.empty())
+ {
+ vector<int> todo;
+ bad_properties.swap(todo);
+
+ int sid = get_bv_sid(1);
+ int cursor = 0;
+
+ while (cursor+1 < GetSize(todo))
+ {
+ int nid_a = todo[cursor++];
+ int nid_b = todo[cursor++];
+ int nid = next_nid++;
+
+ bad_properties.push_back(nid);
+ btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
+ }
+
+ if (!bad_properties.empty()) {
+ if (cursor < GetSize(todo))
+ bad_properties.push_back(todo[cursor++]);
+ log_assert(cursor == GetSize(todo));
+ } else {
+ int nid = next_nid++;
+ log_assert(cursor == 0);
+ log_assert(GetSize(todo) == 1);
+ btorf("%d bad %d\n", nid, todo[cursor]);
}
}
}
struct BtorBackend : public Backend {
BtorBackend() : Backend("btor", "write design to BTOR file") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" -v\n");
log(" Add comments and indentation to BTOR output file\n");
log("\n");
+ log(" -s\n");
+ log(" Output only a single bad property for all asserts\n");
+ log("\n");
}
- virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- bool verbose = false;
+ bool verbose = false, single_bad = false;
log_header(design, "Executing BTOR backend.\n");
verbose = true;
continue;
}
+ if (args[argidx] == "-s") {
+ single_bad = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx);
*f << stringf("; BTOR description generated by %s for module %s.\n",
yosys_version_str, log_id(topmod));
- BtorWorker(*f, topmod, verbose);
+ BtorWorker(*f, topmod, verbose, single_bad);
*f << stringf("; end of yosys output\n");
}
projects / yosys.git / blobdiff