Merge pull request #2485 from whitequark/cxxrtl-cell-input-buffering

[yosys.git] / backends / cxxrtl / cxxrtl_capi.h

diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h
index 385d6dcf386080c80a878ac34a9979807984bb8d..d67c58f94d1f64087bb72a7050179a706c2cf14a 100644 (file)
--- a/backends/cxxrtl/cxxrtl_capi.h
+++ b/backends/cxxrtl/cxxrtl_capi.h
@@ -52,9 +52,23 @@ typedef struct _cxxrtl_handle *cxxrtl_handle;
 // The `design` is consumed by this operation and cannot be used afterwards.
 cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);
 
+// Create a design handle at a given hierarchy position from a design toplevel.
+//
+// This operation is similar to `cxxrtl_create`, except the full hierarchical name of every object
+// is prepended with `root`.
+cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *root);
+
 // Release all resources used by a design and its handle.
 void cxxrtl_destroy(cxxrtl_handle handle);
 
+// Reinitialize the design, replacing the internal state with the reset values while preserving
+// black boxes.
+//
+// This operation is essentially equivalent to a power-on reset. Values, wires, and memories are
+// returned to their reset state while preserving the state of black boxes and keeping all of
+// the interior pointers obtained with e.g. `cxxrtl_get` valid.
+void cxxrtl_reset(cxxrtl_handle handle);
+
 // Evaluate the design, propagating changes on inputs to the `next` value of internal state and
 // output wires.
 //