enable_upto = True
enable_offset = True
+enable_hierarchy = True
+enable_logic = True
def make_module(f, modname, width, subs):
print("module %s (A, B, C, X, Y, Z);" % modname, file=f)
if submod is None or 3*subs[submod] >= len(outbits):
for bit in outbits:
- print(" assign %s = %s;" % (bit, np.random.choice(inbits)), file=f)
+ if enable_logic:
+ print(" assign %s = %s & ~%s;" % (bit, np.random.choice(inbits), np.random.choice(inbits)), file=f)
+ else:
+ print(" assign %s = %s;" % (bit, np.random.choice(inbits)), file=f)
break
instidx += 1
print("endmodule", file=f)
with open("test_top.v", "w") as f:
- make_module(f, "sub1", 2, {})
- make_module(f, "sub2", 3, {})
- make_module(f, "sub3", 4, {})
- make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
- make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
- make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
- make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8})
-
-os.system("set -x; ../../yosys -p 'prep -top top; write_edif -pvector par test_syn.edif' test_top.v")
+ if enable_hierarchy:
+ make_module(f, "sub1", 2, {})
+ make_module(f, "sub2", 3, {})
+ make_module(f, "sub3", 4, {})
+ make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
+ make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
+ make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
+ make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8})
+ else:
+ make_module(f, "top", 32, {})
+
+os.system("set -x; ../../yosys -p 'synth_xilinx -top top; write_edif -pvector par test_syn.edif' test_top.v")
with open("test_syn.tcl", "w") as f:
print("read_edif test_syn.edif", file=f)