Formatting fixes

[yosys.git] / backends / firrtl / firrtl.cc

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 21eade1fce7b6a43ec7c348a0ec51d160e44e870..e83d4f654bd8339918f90a909b019f392f6267a4 100644 (file)
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -306,17 +306,8 @@ struct FirrtlWorker
                // If this is a parameterized module, its parent module is encoded in the cell type
                if (cell->type.begins_with("$paramod"))
                {
-                       std::string::iterator it;
-                       for (it = cell_type.begin(); it < cell_type.end(); it++)
-                       {
-                               switch (*it) {
-                                       case '\\': /* FALL_THROUGH */
-                                       case '=': /* FALL_THROUGH */
-                                       case '\'': /* FALL_THROUGH */
-                                       case '$': instanceOf.append("_"); break;
-                                       default: instanceOf.append(1, *it); break;
-                               }
-                       }
+                       log_assert(cell->has_attribute(ID::hdlname));
+                       instanceOf = cell->get_string_attribute(ID::hdlname);
                }
                else
                {
@@ -401,7 +392,34 @@ struct FirrtlWorker
                return result;
        }
 
-       void run()
+       void emit_extmodule()
+       {
+               std::string moduleFileinfo = getFileinfo(module);
+               f << stringf("  extmodule %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
+               vector<std::string> port_decls;
+
+               for (auto wire : module->wires())
+               {
+                       const auto wireName = make_id(wire->name);
+                       std::string wireFileinfo = getFileinfo(wire);
+
+                       if (wire->port_input && wire->port_output)
+                       {
+                               log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
+                       }
+                       port_decls.push_back(stringf("    %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
+                                       wireName, wire->width, wireFileinfo.c_str()));
+               }
+
+               for (auto &str : port_decls)
+               {
+                       f << str;
+               }
+
+               f << stringf("\n");
+       }
+
+       void emit_module()
        {
                std::string moduleFileinfo = getFileinfo(module);
                f << stringf("  module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
@@ -504,8 +522,8 @@ struct FirrtlWorker
                                continue;
                        }
                        if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
-                                                                                               ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
-                                                                                               ID($logic_and), ID($logic_or), ID($pow)))
+                                        ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
+                                        ID($logic_and), ID($logic_or), ID($pow)))
                        {
                                string a_expr = make_expr(cell->getPort(ID::A));
                                string b_expr = make_expr(cell->getPort(ID::B));
@@ -593,7 +611,7 @@ struct FirrtlWorker
                                        primop = "eq";
                                        always_uint = true;
                                        firrtl_width = 1;
-                           }
+                               }
                                else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
                                        primop = "neq";
                                        always_uint = true;
@@ -1085,6 +1103,18 @@ struct FirrtlWorker
 
                for (auto str : wire_exprs)
                        f << str;
+
+               f << stringf("\n");
+       }
+
+       void run()
+       {
+               // Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
+               // emitted in such a case.
+               if (module->get_blackbox_attribute())
+                       emit_extmodule();
+               else
+                       emit_module();
        }
 };