Merge remote-tracking branch 'origin/master' into eddie/fix_1262

[yosys.git] / backends / intersynth / intersynth.cc

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 97ead3c64efa58901eea6310d2408d3eb2bb2ecb..809a0fa09a8bc76035f78ee492b3aedb49487a37 100644 (file)
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -24,6 +24,8 @@
 #include "kernel/log.h"
 #include <string>
 
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
 
 static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
 {
@@ -44,7 +46,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
 
 struct IntersynthBackend : public Backend {
        IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
-       virtual void help()
+       void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -69,9 +71,9 @@ struct IntersynthBackend : public Backend {
                log("http://www.clifford.at/intersynth/\n");
                log("\n");
        }
-       virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
-               log_header("Executing INTERSYNTH backend.\n");
+               log_header(design, "Executing INTERSYNTH backend.\n");
                log_push();
 
                std::vector<std::string> libfiles;
@@ -101,17 +103,17 @@ struct IntersynthBackend : public Backend {
                log("Output filename: %s\n", filename.c_str());
 
                for (auto filename : libfiles) {
-                       FILE *f = fopen(filename.c_str(), "rt");
-                       if (f == NULL)
+                       std::ifstream f;
+                       f.open(filename.c_str());
+                       if (f.fail())
                                log_error("Can't open lib file `%s'.\n", filename.c_str());
                        RTLIL::Design *lib = new RTLIL::Design;
-                       Frontend::frontend_call(lib, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+                       Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
                        libs.push_back(lib);
-                       fclose(f);
                }
 
                if (libs.size() > 0)
-                       log_header("Continuing INTERSYNTH backend.\n");
+                       log_header(design, "Continuing INTERSYNTH backend.\n");
 
                std::set<std::string> conntypes_code, celltypes_code;
                std::string netlists_code;
@@ -125,7 +127,7 @@ struct IntersynthBackend : public Backend {
                        RTLIL::Module *module = module_it.second;
                        SigMap sigmap(module);
 
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_blackbox_attribute())
                                continue;
                        if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
                                continue;
@@ -157,7 +159,7 @@ struct IntersynthBackend : public Backend {
                                }
                        }
 
-                       // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types 
+                       // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
                        for (auto cell_it : module->cells_)
                        {
                                RTLIL::Cell *cell = cell_it.second;
@@ -181,7 +183,7 @@ struct IntersynthBackend : public Backend {
                                        if (param.second.bits.size() != 32) {
                                                node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
                                                for (int i = param.second.bits.size()-1; i >= 0; i--)
-                                                       node_code += param.second.bits[i] == RTLIL::S1 ? "1" : "0";
+                                                       node_code += param.second.bits[i] == State::S1 ? "1" : "0";
                                        } else
                                                node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
                                }
@@ -215,3 +217,4 @@ struct IntersynthBackend : public Backend {
        }
 } IntersynthBackend;
 
+PRIVATE_NAMESPACE_END