Fix handling of some formal cells in btor back-end

[yosys.git] / backends / rtlil / rtlil_backend.cc

diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index a6e45b2f2e9e09ce35207cf057e847127dd67e9a..1b11de5ec39454df7e759c8a9e111acc1b1984ef 100644 (file)
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -51,15 +51,19 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
                        }
                }
                f << stringf("%d'", width);
-               for (int i = offset+width-1; i >= offset; i--) {
-                       log_assert(i < (int)data.bits.size());
-                       switch (data.bits[i]) {
-                       case State::S0: f << stringf("0"); break;
-                       case State::S1: f << stringf("1"); break;
-                       case RTLIL::Sx: f << stringf("x"); break;
-                       case RTLIL::Sz: f << stringf("z"); break;
-                       case RTLIL::Sa: f << stringf("-"); break;
-                       case RTLIL::Sm: f << stringf("m"); break;
+               if (data.is_fully_undef()) {
+                       f << "x";
+               } else {
+                       for (int i = offset+width-1; i >= offset; i--) {
+                               log_assert(i < (int)data.bits.size());
+                               switch (data.bits[i]) {
+                               case State::S0: f << stringf("0"); break;
+                               case State::S1: f << stringf("1"); break;
+                               case RTLIL::Sx: f << stringf("x"); break;
+                               case RTLIL::Sz: f << stringf("z"); break;
+                               case RTLIL::Sa: f << stringf("-"); break;
+                               case RTLIL::Sm: f << stringf("m"); break;
+                               }
                        }
                }
        } else {
@@ -354,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
 
                bool first_conn_line = true;
                for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
-                       bool show_conn = !only_selected;
-                       if (only_selected) {
+                       bool show_conn = !only_selected || design->selected_whole_module(module->name);
+                       if (!show_conn) {
                                RTLIL::SigSpec sigs = it->first;
                                sigs.append(it->second);
                                for (auto &c : sigs.chunks()) {