pass metadata: fixed some of the output formatting

[yosys.git] / backends / simplec / simplec.cc

diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index 83ed5e6e0725d6761f7616b7bfa9b22ed8677b51..e283dcf7c1776d899c570596b1af71affd1cf1bb 100644 (file)
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -744,7 +744,7 @@ struct SimplecWorker
 
 struct SimplecBackend : public Backend {
        SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -763,7 +763,7 @@ struct SimplecBackend : public Backend {
                log("THIS COMMAND IS UNDER CONSTRUCTION\n");
                log("\n");
        }
-       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
        {
                reserved_cids.clear();
                id2cid.clear();