cxxrtl: make alias analysis outlining-aware.
[yosys.git] / backends / smv / smv.cc
index 7113ebc97f0bfe89a76d0cf266fdd6389ef5d29d..4e5c6050db61be169b5d7c9105fc7412dd2195e6 100644 (file)
@@ -358,7 +358,8 @@ struct SmvWorker
                                continue;
                        }
 
-                       if (cell->type.in(ID($div), ID($mod)))
+                       // SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all
+                       if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/))
                        {
                                int width_y = GetSize(cell->getPort(ID::Y));
                                int width = max(width_y, GetSize(cell->getPort(ID::A)));
@@ -366,7 +367,7 @@ struct SmvWorker
                                string expr_a, expr_b, op;
 
                                if (cell->type == ID($div))  op = "/";
-                               if (cell->type == ID($mod))  op = "mod";
+                               //if (cell->type == ID($mod))  op = "mod";
 
                                if (cell->getParam(ID::A_SIGNED).as_bool())
                                {
@@ -701,7 +702,7 @@ struct SmvWorker
 
 struct SmvBackend : public Backend {
        SmvBackend() : Backend("smv", "write design to SMV file") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -719,7 +720,7 @@ struct SmvBackend : public Backend {
                log("THIS COMMAND IS UNDER CONSTRUCTION\n");
                log("\n");
        }
-       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
        {
                std::ifstream template_f;
                bool verbose = false;