Merge pull request #3080 from YosysHQ/micko/init_wire

[yosys.git] / backends / verilog / verilog_backend.cc

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6fb14d7fc8455a193fb4ca4c7c6cecbce0274453..47ef1c479d97d01bcdceb8609ade8e006395adb7 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -44,6 +44,7 @@ std::string auto_prefix, extmem_prefix;
 RTLIL::Module *active_module;
 dict<RTLIL::SigBit, RTLIL::State> active_initdata;
 SigMap active_sigmap;
+IdString initial_id;
 
 void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
 {
@@ -1943,7 +1944,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 
        f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*");
        if (!systemverilog)
-               f << indent + "  " << "if (" << id("\\initial") << ") begin end\n";
+               f << indent + "  " << "if (" << id(initial_id) << ") begin end\n";
        dump_case_body(f, indent, &proc->root_case, true);
 
        std::string backup_indent = indent;
@@ -2062,6 +2063,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
        dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true);
        f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
        bool keep_running = true;
+       int cnt = 0;
        for (int port_id = 1; keep_running; port_id++) {
                keep_running = false;
                for (auto wire : module->wires()) {
@@ -2070,14 +2072,16 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
                                        f << stringf(", ");
                                f << stringf("%s", id(wire->name).c_str());
                                keep_running = true;
+                               if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
                                continue;
                        }
                }
        }
        f << stringf(");\n");
-
-       if (!systemverilog && !module->processes.empty())
-               f << indent + "  " << "reg " << id("\\initial") << " = 0;\n";
+       if (!systemverilog && !module->processes.empty()) {
+               initial_id = NEW_ID;
+               f << indent + "  " << "reg " << id(initial_id) << " = 0;\n";
+       }
 
        for (auto w : module->wires())
                dump_wire(f, indent + "  ", w);