/* BFD library support routines for architectures.
- Copyright (C) 1990-2020 Free Software Foundation, Inc.
+ Copyright (C) 1990-2021 Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
. bfd_arch_k1om, {* Intel K1OM. *}
.#define bfd_mach_k1om (1 << 6)
.#define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax)
-.#define bfd_mach_i386_nacl (1 << 7)
-.#define bfd_mach_i386_i386_nacl (bfd_mach_i386_i386 | bfd_mach_i386_nacl)
-.#define bfd_mach_x86_64_nacl (bfd_mach_x86_64 | bfd_mach_i386_nacl)
-.#define bfd_mach_x64_32_nacl (bfd_mach_x64_32 | bfd_mach_i386_nacl)
. bfd_arch_iamcu, {* Intel MCU. *}
.#define bfd_mach_iamcu (1 << 8)
.#define bfd_mach_i386_iamcu (bfd_mach_i386_i386 | bfd_mach_iamcu)
.#define bfd_mach_iq10 2
. bfd_arch_bpf, {* Linux eBPF. *}
.#define bfd_mach_bpf 1
+.#define bfd_mach_xbpf 2
. bfd_arch_epiphany, {* Adapteva EPIPHANY. *}
.#define bfd_mach_epiphany16 1
.#define bfd_mach_epiphany32 2
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
.#define bfd_mach_xtensa 1
. bfd_arch_z80,
-.#define bfd_mach_z80strict 1 {* Zilog Z80 without undocumented opcodes. *}
-.#define bfd_mach_z180 2 {* Zilog Z180: successor with additional instructions, but without halves of ix and iy *}
-.#define bfd_mach_z80 3 {* Zilog Z80 with ixl, ixh, iyl, and iyh. *}
-.#define bfd_mach_ez80_z80 4 {* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
-.#define bfd_mach_ez80_adl 5 {* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
-.#define bfd_mach_z80n 6 {* Z80N *}
-.#define bfd_mach_z80full 7 {* Zilog Z80 with all undocumented instructions. *}
-.#define bfd_mach_gbz80 8 {* GameBoy Z80 (reduced instruction set) *}
-.#define bfd_mach_r800 11 {* Ascii R800: successor with multiplication. *}
+.{* Zilog Z80 without undocumented opcodes. *}
+.#define bfd_mach_z80strict 1
+.{* Zilog Z180: successor with additional instructions, but without
+. halves of ix and iy. *}
+.#define bfd_mach_z180 2
+.{* Zilog Z80 with ixl, ixh, iyl, and iyh. *}
+.#define bfd_mach_z80 3
+.{* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode. *}
+.#define bfd_mach_ez80_z80 4
+.{* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode. *}
+.#define bfd_mach_ez80_adl 5
+.{* Z80N *}
+.#define bfd_mach_z80n 6
+.{* Zilog Z80 with all undocumented instructions. *}
+.#define bfd_mach_z80full 7
+.{* GameBoy Z80 (reduced instruction set). *}
+.#define bfd_mach_gbz80 8
+.{* ASCII R800: successor with multiplication. *}
+.#define bfd_mach_r800 11
. bfd_arch_lm32, {* Lattice Mico32. *}
.#define bfd_mach_lm32 1
. bfd_arch_microblaze,{* Xilinx MicroBlaze. *}
.#define bfd_mach_tilegx32 2
. bfd_arch_aarch64, {* AArch64. *}
.#define bfd_mach_aarch64 0
+.#define bfd_mach_aarch64_8R 1
.#define bfd_mach_aarch64_ilp32 32
. bfd_arch_nios2, {* Nios II. *}
.#define bfd_mach_nios2 0
.#define bfd_mach_ck803 5
.#define bfd_mach_ck807 6
.#define bfd_mach_ck810 7
+.#define bfd_mach_ck860 8
. bfd_arch_last
. };
*/
const char **name_ptr;
const char **name_list;
const bfd_arch_info_type * const *app;
- bfd_size_type amt;
+ size_t amt;
/* Determine the number of architectures. */
vec_length = 0;