#define BFD_DEFAULT_TARGET_SIZE @bfd_default_target_size@
#define BFD_HOST_64BIT_LONG @BFD_HOST_64BIT_LONG@
+#define BFD_HOST_LONG_LONG @BFD_HOST_LONG_LONG@
#if @BFD_HOST_64_BIT_DEFINED@
#define BFD_HOST_64_BIT @BFD_HOST_64_BIT@
#define BFD_HOST_U_64_BIT @BFD_HOST_U_64_BIT@
/* Support for different sizes of target format ints and addresses.
If the type `long' is at least 64 bits, BFD_HOST_64BIT_LONG will be
- set to 1 above. Otherwise, if gcc is being used, this code will
- use gcc's "long long" type. Otherwise, BFD_HOST_64_BIT must be
- defined above. */
+ set to 1 above. Otherwise, if the host compiler used during
+ configuration supports long long, this code will use it.
+ Otherwise, BFD_HOST_64_BIT must be defined above. */
#ifndef BFD_HOST_64_BIT
# if BFD_HOST_64BIT_LONG
# define BFD_HOST_64_BIT long
# define BFD_HOST_U_64_BIT unsigned long
# else
-# ifdef __GNUC__
-# if __GNUC__ >= 2
+# if BFD_HOST_LONG_LONG
# define BFD_HOST_64_BIT long long
# define BFD_HOST_U_64_BIT unsigned long long
-# endif /* __GNUC__ >= 2 */
-# endif /* ! defined (__GNUC__) */
+# endif /* ! BFD_HOST_LONG_LONG */
# endif /* ! BFD_HOST_64BIT_LONG */
#endif /* ! defined (BFD_HOST_64_BIT) */
extern bfd_vma bfd_h8300_pad_address
(bfd *, bfd_vma);
+/* IA64 Itanium code generation. Called from linker. */
+extern void bfd_elf32_ia64_after_parse
+ (int);
+
+extern void bfd_elf64_ia64_after_parse
+ (int);
+
/* Extracted from init.c. */
void bfd_init (void);
#define BFD_IND_SECTION_NAME "*IND*"
/* The absolute section. */
-extern const asection bfd_abs_section;
+extern asection bfd_abs_section;
#define bfd_abs_section_ptr ((asection *) &bfd_abs_section)
#define bfd_is_abs_section(sec) ((sec) == bfd_abs_section_ptr)
/* Pointer to the undefined section. */
-extern const asection bfd_und_section;
+extern asection bfd_und_section;
#define bfd_und_section_ptr ((asection *) &bfd_und_section)
#define bfd_is_und_section(sec) ((sec) == bfd_und_section_ptr)
/* Pointer to the common section. */
-extern const asection bfd_com_section;
+extern asection bfd_com_section;
#define bfd_com_section_ptr ((asection *) &bfd_com_section)
/* Pointer to the indirect section. */
-extern const asection bfd_ind_section;
+extern asection bfd_ind_section;
#define bfd_ind_section_ptr ((asection *) &bfd_ind_section)
#define bfd_is_ind_section(sec) ((sec) == bfd_ind_section_ptr)
extern const struct symbol_cache_entry * const bfd_und_symbol;
extern const struct symbol_cache_entry * const bfd_ind_symbol;
#define bfd_get_section_size_before_reloc(section) \
- ((section)->reloc_done ? (abort (), (bfd_size_type) 1) \
- : (section)->_raw_size)
+ ((section)->_raw_size)
#define bfd_get_section_size_after_reloc(section) \
((section)->reloc_done ? (section)->_cooked_size \
: (abort (), (bfd_size_type) 1))
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
+#define bfd_mach_mipsisa64r2 65
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 1
#define bfd_mach_i386_i8086 2
#define bfd_mach_rs6k_rsc 6003
#define bfd_mach_rs6k_rs2 6002
bfd_arch_hppa, /* HP PA RISC */
+#define bfd_mach_hppa10 10
+#define bfd_mach_hppa11 11
+#define bfd_mach_hppa20 20
+#define bfd_mach_hppa20w 25
bfd_arch_d10v, /* Mitsubishi D10V */
#define bfd_mach_d10v 1
#define bfd_mach_d10v_ts2 2
bfd_arch_v850, /* NEC V850 */
#define bfd_mach_v850 1
#define bfd_mach_v850e 'E'
+#define bfd_mach_v850e1 '1'
bfd_arch_arc, /* ARC Cores */
#define bfd_mach_arc_5 5
#define bfd_mach_arc_6 6
#define bfd_mach_fr400 400
#define bfd_mach_frvtomcat 499 /* fr500 prototype */
#define bfd_mach_fr500 500
+#define bfd_mach_fr550 550
bfd_arch_mcore,
bfd_arch_ia64, /* HP/Intel ia64 */
#define bfd_mach_ia64_elf64 64
bfd_arch_xstormy16,
#define bfd_mach_xstormy16 1
bfd_arch_msp430, /* Texas Instruments MSP430 architecture. */
-#define bfd_mach_msp110 110
#define bfd_mach_msp11 11
+#define bfd_mach_msp110 110
#define bfd_mach_msp12 12
#define bfd_mach_msp13 13
#define bfd_mach_msp14 14
-#define bfd_mach_msp41 41
+#define bfd_mach_msp15 15
+#define bfd_mach_msp16 16
#define bfd_mach_msp31 31
#define bfd_mach_msp32 32
#define bfd_mach_msp33 33
+#define bfd_mach_msp41 41
+#define bfd_mach_msp42 42
#define bfd_mach_msp43 43
#define bfd_mach_msp44 44
-#define bfd_mach_msp15 15
-#define bfd_mach_msp16 16
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_last
BFD_RELOC_MIPS_RELGOT,
BFD_RELOC_MIPS_JALR,
+
/* Fujitsu Frv Relocations. */
BFD_RELOC_FRV_LABEL16,
BFD_RELOC_FRV_LABEL24,
BFD_RELOC_FRV_GPRELHI,
BFD_RELOC_FRV_GPRELLO,
+
/* This is a 24bit GOT-relative reloc for the mn10300. */
BFD_RELOC_MN10300_GOTOFF24,
/* Entry points used for symbols. */
#define BFD_JUMP_TABLE_SYMBOLS(NAME) \
NAME##_get_symtab_upper_bound, \
- NAME##_get_symtab, \
+ NAME##_canonicalize_symtab, \
NAME##_make_empty_symbol, \
NAME##_print_symbol, \
NAME##_get_symbol_info, \
/* Data for use by back-end routines, which isn't
generic enough to belong in this structure. */
- void *backend_data;
+ const void *backend_data;
} bfd_target;