Fix bug in PDP11 assembler when handling a JSr instruction with deferred auto increment.

[binutils-gdb.git] / bfd / config.bfd

diff --git a/bfd/config.bfd b/bfd/config.bfd
index 0db8ed4562b2c11ce51e6a3b138c317f4014a1aa..0e397f540b625e9ce6d6541d6529a970d4a2c3c2 100644 (file)
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -170,6 +170,7 @@ c54x*)               targ_archs=bfd_tic54x_arch ;;
 cr16*)          targ_archs=bfd_cr16_arch ;;
 crisv32)        targ_archs=bfd_cris_arch ;;
 crx*)           targ_archs=bfd_crx_arch ;;
+csky*)          targ_archs=bfd_csky_arch ;;
 dlx*)           targ_archs=bfd_dlx_arch ;;
 fido*)          targ_archs=bfd_m68k_arch ;;
 hppa*)          targ_archs=bfd_hppa_arch ;;
@@ -461,6 +462,11 @@ case "${targ}" in
     targ_underscore=yes
     ;;
 
+  csky-*-elf* | csky-*-linux* )
+    targ_defvec=csky_elf32_be_vec
+    targ_selvecs="csky_elf32_be_vec csky_elf32_le_vec"
+    ;;
+
   d10v-*-*)
     targ_defvec=d10v_elf32_vec
     ;;
@@ -665,6 +671,10 @@ case "${targ}" in
   x86_64-*-elf* | x86_64-*-rtems* | x86_64-*-fuchsia)
     targ_defvec=x86_64_elf64_vec
     targ_selvecs="i386_elf32_vec iamcu_elf32_vec x86_64_elf32_vec l1om_elf64_vec k1om_elf64_vec"
+    case "${targ}" in
+      x86_64-*-rtems*)
+    targ_selvecs="${targ_selvecs} x86_64_pei_vec"
+    esac
     want64=true
     ;;
   x86_64-*-dragonfly*)
@@ -1170,12 +1180,12 @@ case "${targ}" in
     ;;
 
 #ifdef BFD64
-  riscv32-*-*)
+  riscv-*-* | riscv32*-*-*)
     targ_defvec=riscv_elf32_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
     want64=true
     ;;
-  riscv64-*-*)
+  riscv64*-*-*)
     targ_defvec=riscv_elf64_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
     want64=true