Fix bug in PDP11 assembler when handling a JSr instruction with deferred auto increment.

[binutils-gdb.git] / bfd / cpu-riscv.c

diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
index a938199889a5d8552dcb414bb74eeabaf32cc461..b2ab7e828e87f696c2be50959713dce2d1e964c9 100644 (file)
--- a/bfd/cpu-riscv.c
+++ b/bfd/cpu-riscv.c
@@ -1,5 +1,5 @@
 /* BFD backend for RISC-V
-   Copyright 2011-2016 Free Software Foundation, Inc.
+   Copyright (C) 2011-2018 Free Software Foundation, Inc.
 
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.