(no commit message)

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index 537db130e35af287328ccc92be419f0da7f3f639..00a2fcc02bbd978e601d65c76d3b4a61d784ab99 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -11,33 +11,37 @@ move things along from one stage to the next
 ## Currently working on
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
-- <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts on university and technical mailing lists
+- <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
-
-- <https://bugs.libre-soc.org/show_bug.cgi?id=394> Reach out to developers of 'BlackParrot' RV64GC Multicore SoC 
-
+- <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL Pipeline unit tests
 
 ## List of things that need more fleshed out bug reports:
 
-* Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+- Scoreboard documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
+
+
+- LDST documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
-* LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
 
 ## Completed but not yet submitted
 
-- Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401>
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
 
 - Coriolis2 documentation and setup scripts
-  <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=404>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=138> 
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
+
+- TRAP pipeline discussion
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
 
 ## Submitted for NLNet RFP